JPS63123212A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To simplify the titled circuit and to obtain the frequency characteristic in following to the frequency of an input signal by adding an input signal to a constant value and applying amplitude limit to the maximum and minimum, value so as to reduce the DC level. CONSTITUTION:A prescribed value alphai is added to input signals Q0-Q7 during the H level period in response to the timing of an added timing signal CAR by an adder circuit 11. The signal is subject to amplitude limit by a value decreased from a maximum value by a prescribed level at a maximum amplitude limit circuit 16 to be a flat level, and fed to a minimum, value limit circuit 17, the amplitude is limited by an AND gate and an OR gate to be a flat level by a level lower than the prescribed level and signals S0-S7 are obtained. The DC level of the signals S0-S7 is decreased by a subtraction circuit 18 and extracted as signals DQ0-DQ7.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a signal processing circuit that removes unnecessary frequency components from an input signal to obtain a signal of a desired frequency. In order to solve the problem of conventional circuits where the amount of delay must be changed when removing a certain frequency component, we developed an adder circuit that adds the input signal and a constant value, and an adder circuit that adds the maximum and minimum values of the output of the adder circuit. By providing a circuit that limits the amplitude of each circuit and a circuit that adjusts the output level of the amplitude υ1 limiting circuit, it is possible to obtain a signal with a desired frequency component without requiring a large-scale configuration for the delay circuit as in conventional circuits. This is what I did.

[Industrial application field]

The present invention relates to a signal processing circuit, and particularly to a signal processing circuit that extracts a signal of a desired frequency component from an input signal, and is applied to digital filters, analog filters, and the like.

[Conventional technology]

As conventional circuits for obtaining delayed signals, for example, analog signal processing circuits using ultrasonic delay lines and the like, and digital signal processing circuits using flip-flop shift registers and the like are known.

FIG. 4 shows a block diagram of a conventional circuit for removing a certain frequency component from an input signal, and FIG. 5 or 6 shows a timing chart of signals of the circuit shown in FIG. 4.

Hereinafter, the signals to be handled will be, for example, digital signals, but since it is difficult to understand the waveforms of digital signals as they are, analog signal waveforms will be used for explanation.

In Figure 4, the input signal V+(j) entering terminal 1
(or V2 (j)) is delayed by a delay device d+ (or C2) in a delay circuit 2 such as a shift register, and becomes a signal X+ (or ×1'), which is added in an adder 3 to produce a signal X2 (or ×2′). signal
2 (or ×2') is attenuated to 1/2 in level by the 1/2 attenuator 4, and becomes the signal Vo+(t) (or Voz(j
)) and is taken out from the terminal 5.

Here, the input signal V+ (t) or V2(t)
'4rvi(t), output signal 13Vo+(j) or VO
If 2(1) is Vo(j) and the delay ffid + or C2 is di, then Vo(i)-1/2(Vi(t-di)+Vi(t))(1) holds true, the above equation Delayed signal Vi(
t-di) to Vi (t-di)=Vi (t)+ai (2
) However, if we set αi=2vi-di/Ti and substitute equation 0 into equation (1), then Vo(j)-1/2(Vi(t)±αi+vi(t))=Vl(
t)±C1 However, C1=(1/2)C1. Here, vi is the peak value of the input signal, and Ti is the period of the input signal.

[Problem that the invention seeks to solve]

The conventional circuit is configured with a circuit using an ultrasonic delay line or a shift register as the delay circuit 2 shown in FIG.
There was a problem that the shape was large and it could not be configured compactly.

Further, in the conventional circuit, when following an input signal and removing a certain frequency component, it is necessary to vary the delay a in the delay circuit 2, which has the problem of cumbersome operation.

[Means for solving problems]

FIG. 1 shows a basic block diagram of the circuit of the present invention.

In the figure, 15 is a constant value α corresponding to the predetermined delay ff1di.
A constant value generating circuit 11 generates input signal Vi(t
)+7) 1/21R Addition n path that adds a constant value αi to the input signal MVi(t) every period, 16.17 is the addition circuit 11
18 is a direct current of the output signal of the amplitude limiting circuit (16, 17); 18 is a DC output signal of the amplitude limiting circuit (16, 17); This is a DC level adjustment circuit that lowers the level.

[Effect]

A signal of a predetermined frequency component is obtained by adding a constant value αi to the input signal Vi (t), limiting the amplitude of its maximum value and minimum value, respectively, and lowering its DC level.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the circuit of the present invention.

Hereinafter, the signals to be handled will be, for example, digital signals, but since it is difficult to understand the waveforms of digital signals as they are, analog signal waveforms will be used for explanation. In the figure, for example, a triangular wave input signal @QO to Q7 (solid line in FIG. 3(D)) inputted to the terminal 10 is supplied to the addition circuit 11, while an addition timing signal inputted to the terminal 12 is It is supplied to the constant value generation circuit 15.

The addition timing signal CAR has a timing corresponding to 1/2 period of the input signal, and is supplied to a constant value generation circuit 15, where a constant value αi is obtained only during the trubel period of the signal CAR. The constant value αi is supplied to the adder circuit 11. In the adder circuit 11, a constant value αi is added to the input signals QO to Q7 only during the trubel period according to the timing of the addition timing signal CAR, and the signals shown by the solid line and the two-dot chain line shown in FIG. 3(B) are extracted. .

This signal is amplitude-limited by the next maximum value amplitude limiting circuit 16 by a predetermined level below the maximum value (the part indicated by the two-dot chain line in <8> in FIG. 3), and is made into a flat level. B)
The signal shown in the solid line is the only signal shown. Furthermore, this signal is supplied to a minimum amplitude limiting circuit 17 including a comparator 17a, where it is compared with the level shown by the dotted chain line in FIG. limited to a flat level.

As a result, the signals SO to S7 shown by solid lines in FIG. 3(C) are obtained.

Signals SO to S7 are subtracted circuit (DC level adjustment circuit) 18
The DC level of the signal is lowered to form the signal DQO-DQ7 shown in FIG. The amount of delay of the output signal DQO-DQ7 with respect to the input signal QO-07 corresponds to the constant value αi, and a desired amount of delay can be obtained by appropriately selecting the constant value αi.

In this way, the triangular wave input signal QO-07 (Fig. 3 (D
) has a constant value αi added to it every 1/2 period, limits its maximum amplitude and minimum amplitude, and shifts its DC level, thereby removing unnecessary frequency components. The signal has a desired frequency.

In this case, when the constant value αi is kept constant, if input signals of different frequencies come in as shown in Figures 5 and 6, the amount of delay will vary accordingly, and the frequency to be removed will be It is possible to obtain an output signal that follows the frequency of the signal and has frequency characteristics according to the frequency characteristics of the input signal. Therefore, a predetermined frequency signal can be obtained without requiring any operations such as changing the number of stages of a shift register or the clock frequency.

The circuit of the present invention can directly obtain the maximum and minimum amplitude-limited signal 5O-87 using the circuit shown in FIG. There is no need to provide a plurality of delay circuits to crush their outputs, and the circuit can be easily configured.

〔Effect of the invention〕

According to the circuit of the present invention, it is possible to obtain a signal with a predetermined frequency component simply by adding the input signal to a constant value, then limiting the amplitude of the maximum and minimum values, and lowering the DC level. As a delay circuit, the circuit can be constructed more easily and inexpensively than conventional circuits such as ultrasonic delay lines and shift registers, and in particular, it is possible to obtain a signal with frequency characteristics that follow the frequency of the input signal. For example, a predetermined frequency signal can be obtained without the need for any operations such as changing the number of stages of a shift register or clock frequency, and furthermore, there is no need to use multiple delay circuits and provide circuits to calculate their respective outputs. However, since a predetermined frequency signal can be obtained directly, this method also has the advantage that the circuit can be easily configured.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the circuit of the present invention, Fig. 2 is a circuit diagram of an embodiment of the circuit of the invention, Fig. 3 is a timing chart of signals of the circuit shown in Fig. 2, and Fig. 4 is a diagram of the conventional circuit. The block diagram, FIGS. 5 and 6, are timing charts of signals of the circuit shown in FIG. 4. In the figure, 10 is a signal input terminal, 11 is an addition circuit, 12 is an addition timing No. 13 input terminal, 15 is a constant value generation circuit, 16 is a maximum amplitude limiting circuit, 17 is a minimum amplitude limiting circuit, and 18 is a subtraction circuit. (DC level adjustment circuit), 19 is an output terminal.

Claims (1)

[Claims] In a signal processing circuit having a function of filtering a signal of a predetermined frequency component from an input signal (Vi(t)), a predetermined amount of delay (
a constant value generating circuit (15) that generates a constant value (αi) corresponding to di); and a constant value generating circuit (15) that generates a constant value (αi) corresponding to An adder circuit (11) that adds the value (αi), and a level that is a predetermined level lower than the maximum value of the output signal of the adder circuit (11) and a level that is a predetermined level increase from the minimum value are respectively amplitude-limited to achieve a flat level. Amplitude limiting circuit (
16, 17); and a DC level adjustment circuit (18) for lowering the DC level of the output signal of the amplitude limiting circuit (16, 17)).