JPS63123210A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To decrease the circuit scale by constituting a signal delay means by an adder/subtractor circuit and an amplitude correction circuit in a signal processing circuit obtaining a prescribed frequency component through the synthesis of an input signal and its delay signal. CONSTITUTION:The adder/subtractor circuit 2 of delay circuits 10-12 adds a prescribed value alphai generated from a constant value generating circuit 4 to an input signal Vi(t) during a half period of the signal Vi(t) subject to binary coding and subtracts the value alphai from the signal Vi(t) at the next half period to retard the signal Vi(t) by a prescribed period. An amplitude correction circuit 6 corrects the distortion for a prescribed period at each half period where the waveform of the adder/subtractor circuit is distorted due to overflow. Then the constitution of the delay circuits 10-12 is made small. The signal Vi(t) is subject to arithmetic operation by an arithmetic circuit 13 together with signals delayed for a prescribed 5 time by delay circuits 10, 11, 12 respectively. Then the arithmetic circuit 13 generates a sinusoidal wave signal of a desired frequency from the input signal (e.g., triangle wave).

Description

[Detailed Description of the Invention] [Summary] The present invention provides a signal processing circuit that removes unnecessary frequency components from an input signal to obtain a signal of a desired frequency, and is configured using an ultrasonic delay line or a shift register as a delay circuit. In order to solve the problem of conventional circuits being large-scale due to the delay circuit, the delay circuit is combined with an adder/subtracter circuit that adds and subtracts the input signal and a constant value, and an adder/subtractor circuit that corrects the output amplitude of the adder/subtracter circuit at a constant cycle. By constructing a circuit that obtains a delayed signal for a signal, and by connecting multiple circuits in parallel to the input, it is possible to generate a signal with a desired frequency component without requiring a large-scale configuration for the delay circuit as in conventional circuits. This is what I did to get it.

[Industrial application field]

The present invention relates to a signal processing circuit, and particularly to a signal processing circuit that extracts a signal of a desired frequency component from an input signal, and is applied to digital filters, analog filters, and the like.

[Conventional technology]

As conventional circuits for obtaining delayed signals, for example, analog signal processing circuits using ultrasonic delay lines and the like, and digital signal processing circuits using flip-flop shift registers and the like are known.

[Problem that the invention seeks to solve]

Conventional circuits using the above ultrasonic delay line have a problem that they are large in size and cannot be configured compactly.

On the other hand, in the conventional circuit using the above shift register, the seventh
As shown in the figure, for example, the amount of delay (i
3 io) To obtain the signal VO3, use three stages of flip 70 tubes, and in the same way, for example, delay the input signal Vi!
In order to receive one signal Vos of (js jo), it is necessary to use five stages of flip-flops, which increases the circuit scale and has the problem that it cannot be constructed compactly.

(Means for solving problems) FIG. 1 shows a block diagram of the principle of the circuit of the present invention.

In the figure, 4 is a constant value generation circuit that generates a constant value αi corresponding to the delay amount di, and 2 is a constant value generating circuit that generates a constant value αi from the input signal Vi(t) every 1/2 cycle of the input signal Vi(t). An addition/subtraction circuit 6 performs subtraction and adds a constant value αi to the input signal Vi(t), and 6 performs period amplitude correction on the output of the addition/subtraction circuit 2 according to the delay amount di every 1/2 cycle of the input signal V1(t). The output signal Vo has an amplitude corresponding to the amplitude of the input signal Vi(t).
(t), and a plurality of delay circuits made up of these are connected in parallel to the input to form delay means (10, 11°12), and 13 is the output of the delay means and the input. This is a calculation means for calculating a signal and extracting a signal of a predetermined frequency component from an input signal.

[Effect]

By adding or subtracting a constant value αi to the input signal Vi(t) every 1/2 period, and by correcting the amplitude every 1/2 period, a delay circuit that obtains delayed signals with different predetermined delays is constructed. A plurality of circuits are connected in parallel and a signal of a predetermined frequency component is obtained by calculating each output of these circuits and an input signal.

〔Example〕

FIG. 2 shows a concrete block diagram of an embodiment of the circuit of the present invention. Hereinafter, the signals to be handled will be, for example, digital signals, but since it is difficult to understand the waveforms of digital signals as they are, analog signal waveforms will be used for explanation.

In the figure, reference numerals 10, 11, and 12 are delay circuits each having a different delay m, and as shown in FIG. Constant value generation circuit 4. Consists of an amplitude correction circuit 6,
It is provided in parallel to the input. The input and the output of each delay circuit 10, 11, 12 are supplied to the arithmetic circuit 13,
Here, various calculations are performed to remove unnecessary frequency components and the signal is extracted.

Here, the delay circuits 10, 11, and 12 in FIG. 2 will be explained. FIG. 3 shows a circuit diagram for one of these delay circuits. For example, the triangular wave input signal QO~Q that entered terminal 1
7 (solid line in FIG. 4(A)) is supplied to the addition/subtraction circuit 2, while the addition/subtraction timing signal SC( σ
) is supplied to the addition/subtraction n circuit 2 and the constant value generation circuit 4.

The timing signal SC(σ) has a timing corresponding to a desired delay date, and is supplied to a constant value generating circuit 4, where a constant value αi, which will be described later, is obtained. Constant value αi is added/subtracted circuit 2
supplied to In the addition/subtraction circuit 2, the input signal QO-
07, the constant value αi is added or subtracted according to the timing of the timing signal SC(σ), and the signals SO to S7 shown by the solid line in FIG. 4(B) are extracted. That is, the timing signal 5C
(Q) While the L level period subtraction (FIG. 4C) is performed, the one rubel period addition is performed. Signal S
O to S7 are signals whose waveforms are distorted for a period corresponding to the delay time from the maximum value point and minimum value point of input signal QO-07, and the distortion values are (0+X) and ((maximum value M)-x). .

The timing signal @501 ((D) in the same figure) taken out from the addition/subtraction circuit 2 has a timing corresponding to the desired amount of delay, and the timing signal @501 ((C) in the same figure) taken out from the terminal 3 has a timing corresponding to the desired delay amount. ) is supplied to the timing signal generation circuit 5 along with
The timing signal 5C2 ((E) in the same figure) is used.

The signal 5o-37 taken out from the addition/subtraction circuit 2 (the same figure (B)
)), the timing signal SC2 ((E) in the same figure) taken out from the timing signal generation circuit 5 is supplied to the amplitude correction circuit 6, and the signals 5o-87 are variously added and subtracted according to the timing of the timing signal SC2. That is, the signal So”Sy
is taken as is during the L level period of the timing signal SC2, while it is taken as the value ((maximum value M) - (distortion value x)) (dotted line in the same figure (B)) during the H level period t+, and the next During the H level period t2, the value of (O+X) (
(B) (broken line), and this process is repeated.

In this way, the signal So''-8y <solid line in FIG. ~S87.

The signals SSO to SS7 are supplied to the amplitude adjustment circuit 7, and the amplitudes of the maximum and minimum values are adjusted depending on the timing of the signal OF ((F) in the same figure) and the signal LJF ((G) in the same figure) from the adjustment signal generation circuit 8. is adjusted, and the delayed signal DQO- is output from terminal 9.
It is taken out as DQ7 (dashed line in FIG. 6(A)). Signals OF and UF are outputted from the adjustment signal generation circuit 8 by the timing signal SC1 taken out from the addition/subtraction circuit 2 ((D) in the same figure).
It is made in accordance with the timing of

In this way, the input signal @QO-07 (solid line in the same figure (A))
are added or subtracted by a constant value αi, and the period amplitude is corrected in accordance with the delay amount di every 1y2 period, so that the signals DQO to DQ7 delayed by a predetermined m (FII1 (B)
(dashed line).

In other words, without using a large-scale circuit such as an ultrasonic delay line or a shift register, it is possible to obtain the delayed signal DQO-DQ7 by simply adding or subtracting a constant value αi to the input signal QO-07 at a predetermined period and then correcting the waveform. I can do it.

Here, let us consider the relationship between the input signal, the amount of delay, and the period. Regarding the input signal waveforms shown by the solid lines in FIGS. 6A to 6C, for example, the sampling timing shown in FIG. 6D (same as the clock CK of the adjustment signal generation circuit 8 in FIG. 3) is Consider the waveforms after each delay. For example, in FIG. 6(A), the input signal is Vi(
t), its peak value is vl, the delay time is d12 period is T+
, if the signal after delay is V(t-di), I V(t-di) = Vi(t)-(±vi/(Ti/2)) ・d
It becomes +. In general, 'J(t-di) di = V1(t)-(±vi/(Ti/2))・
d1=V 1(t)±2vi ・(d+/Ti)
becomes. Here, if we set 2■i ・(d+/T = αi), then V(t-di) = V 1(t)±αi(1).αi is the constant value mentioned above, and as shown in Fig. 3 This value is added to or subtracted from the input signal in the intermediate addition/subtraction circuit 2.

Input signal V2 (t) shown in FIGS. 6(B) and (C).

The above equation (1) can also be applied to V3(j), and each delay time d2. Delay signal ■d2 (t-dz
>, V (t-d3) can be obtained.

In the above equation (1), if the constant value αi is set constant and the period Ti of the input signal Vi(t) changes, then (
Each input signal V'+ (t) shown in FIGS. 6(A) to (C)
, V2 (t) , V3 (t) ), a: =
Among 2vi - (di /Ti), vi is constant, and the period 1-i and the delay time di change in proportion to each other.

That is, in FIGS. 6(A) to (C), if a constant value αi is set, an output signal vdi (t-di) with a delay time di corresponding to the period (Ti) of the input signal Vi(t) is obtained. be able to. Therefore, when input signals with different frequencies are delayed by a delay interval corresponding to the frequency, conventional circuits change the number of shift register stages, or
Whereas the clock frequency had to be changed, the present invention does not require any such operations.

Returning to the block diagram shown in FIG. Delay circuit 10°11.
The twelve delay amounts dx, d, d2 are created by setting the constant value αi of the constant value generating circuit 4 in FIG. 3, respectively. In this case, the signals 5C (Q) and SC (σ) in FIG.
Various αi can be obtained by simply changing the combination of the level input and L level input terminals. Input signal x (5th
) is delayed by a delay of 1 dx in the delay circuit 10 to become a signal a (Fig. 5), delayed by a delay amount dy in the delay circuit 11 to become a signal b (Fig. 5), and then delayed by a delay circuit 12 by 1 d2. The signal C (FIG. 5) is delayed by .

Signals a and b are supplied to an adder 14 and a 1/2 attenuator 15 of an arithmetic circuit 13 and are computed to become a signal e (FIG. 5).
The signal C and the input signal X are sent to the adder 16.1 of the arithmetic circuit 13.
The signal is supplied to the /2 attenuator 17 and calculated to produce a signal f (FIG. 5). Signals e and f are added to adder 18.1/2 attenuator 1
Supplied to 9 and 81! The signal Y is calculated and output.

Due to its properties, the triangular wave input signal X is generally X(t)
-A+ cosω,) t -1-A 3 CO33
It includes odd harmonic components of ω, 1+Ascos5ω, 1 +.... In the present invention, harmonics, which are unnecessary frequency components, are removed from the input signal X, and an output signal Y having a substantially sinusoidal waveform is obtained.

In this case, each delay amount of the delay circuit 10.11.12 is varied according to the frequency of the input signal, the frequency to be removed follows the frequency of the input signal, and the output has frequency characteristics according to the frequency characteristics of the input signal. I can get a signal.

It should be noted that the number of stages of the delay circuit is not limited to three stages as in the above embodiment, but is appropriately set depending on the frequency characteristics to be obtained.

〔Effect of the invention〕

According to the circuit of the present invention, a predetermined frequency signal can be obtained by simply connecting in parallel a delay circuit that adds or subtracts an input signal to a constant value and then corrects the amplitude of the input signal. The circuit can be configured more easily and inexpensively than conventional circuits using shift registers, etc., and in particular,
Since it is possible to obtain a signal with frequency characteristics that follow the frequency of the input signal, it is possible to obtain a predetermined frequency signal without the need for any operations such as changing the number of stages of a shift register or the clock frequency. It has characteristics.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the circuit of the present invention, FIG. 2 is a concrete block diagram of the circuit of the present invention, FIG. 3 is a circuit diagram of a main part of an embodiment of the circuit of the present invention, and FIG. Fig. 5 is a signal timing chart of the block diagram shown in Fig. 2, Fig. 6 is a diagram showing the relationship between input signals, delay amounts, and periods, and Fig. 7 is a diagram of the shift register. It is a figure explaining the number of stages. In the figure, 1 is a signal input terminal, 2 is an addition/subtraction circuit, 3 is a timing signal input terminal, 4 is a constant value generation circuit, 5 is a timing signal generation circuit, 6 is an amplitude correction circuit, 7 is an amplitude adjustment circuit, and 8 is an adjustment 10.11.12 is a delay circuit; 13 is an arithmetic circuit; 14.16.18 is an adder; 15.17.19 is a 1/2 attenuator. 92 Figures 1 Figure 2

Claims (1)

[Claims] In a signal processing circuit having a function of filtering a signal of a predetermined frequency component from an input signal (Vi(t)), a predetermined amount of delay (
a constant value generating circuit (4) that generates a constant value (αi) corresponding to Constant value(
an addition/subtraction circuit (2) that subtracts αi) and adds the constant value (αi) to the input signal (Vi(t)); 1
an amplitude correction circuit (6) that corrects the amplitude for a period corresponding to the delay amount (di) every /2 period to obtain an output signal (V_0(t)) with an amplitude corresponding to the amplitude of the input signal (Vi(t)); )
a delay means (10, 11, 12) in which a plurality of delay circuits are connected in parallel to the input, and the output of the delay means (10, 11, 12) and the input signal (Vi(t) ) and calculate the above input signal (Vi(t)
) calculation means (13) for extracting a signal of a predetermined frequency component from
A signal processing circuit characterized by: