JPS63123211A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a frequency characteristic signal in following to an input signal frequency by adding an input signal and a prescribed value and extracting a prescribed frequency component from the input signal and a filter output subject to amplitude limit while its maximum and minimum value are adjusted. CONSTITUTION:Each delay of filter circuits 10, 11, 12 is formed by setting a prescribed value alphai of a constant value generating circuit 25 respectively. An input signal X is retarded by the circuit 10 with a delay of 1/2(dx+1) to be a signal (a), to be a signal (b) by the circuit 11 with a delay of 1/2(dy+1) and to be a signal (c) at the circuit 12 by a delay of 1/2(dz+1). The signals a,b are added by an adder 30 by an arithmetic circuit 17 to be a signal (d), a signal (x) is inverted by an inverter 31, added to the signal (d) by an adder 32 to be a signal (e). The signals e,c are fed to an adder 33 and a 1/2 subtractor 34 to be a signal Y from which harmonics are eliminated.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a signal processing circuit that removes unnecessary frequency components from an input signal to obtain a signal of a desired frequency. In order to solve the problem of conventional circuits where the delay a must be changed when removing a certain frequency component, the filter circuit is replaced with an adder circuit that adds the input signal and a constant value, and a maximum value of the output of the adder circuit. It consists of a circuit that limits the amplitude of the amplitude limiter and the minimum value, and a circuit that adjusts the output level of the amplitude limiter circuit, and by providing multiple circuits in parallel with respect to the input, the delay circuit of the filter circuit can be used in a conventional circuit. The present invention is designed to obtain a signal of a desired frequency component without requiring such a large-scale configuration.

[Industrial application field]

The present invention relates to a signal processing circuit, and particularly to a signal processing circuit that extracts a signal of a desired frequency component from an input signal, and is applied to digital filters, analog filters, and the like.

(Prior Art) As conventional circuits that use one delayed signal, for example, analog signal processing circuits using an ultrasonic delay line, etc., and digital signal processing circuits using a shift register using a flip 70 tube, etc. are known. There is.

FIG. 6 shows a block diagram of a conventional circuit for removing a certain frequency component from an input signal, and FIG. 7 or 8 shows a timing chart of signals of the circuit shown in FIG. 6.

Hereinafter, the signals to be handled will be, for example, digital signals, but since it is difficult to understand the waveforms of digital signals as they are, analog signal waveforms will be used for explanation.

In FIG. 6, the input signal V+ (
j) (or V2(j)) is delayed by ff1d+ (or (jz)) in a delay circuit 2 such as a shift register, and is made into a signal X+ (or X1'), which is added in a adder 3 to become a signal (or X2').The signal X2 (or
z(i)) and is taken out from the terminal 5.

Now, change the input signal V+ (t) or V2 (t) to V
i (t), output signal Vo+(j) or VO2(t)e
Vo (t), l extension ff1d+ Matahadz wod i
Then, the delay signal ■1(t-
di) to Vi (t-di)=Vi (t)tcri ■
However, if we set C1-2vi-di/Ti and substitute equation 0 into equation (1), then Vo(j)=1/2 (Vi (t)±αi+Vi(t))-V
i(t) 1C1 However, C1-(1/2)αi. Here, vi is the peak value of the input signal, and T1 is the period of the input signal.

[Problem that the invention seeks to solve]

The conventional circuit is configured with a circuit using an ultrasonic delay line or a shift register as the delay circuit 2 shown in FIG.
There was a problem that the shape was large and it could not be configured compactly. In a conventional circuit using a shift register, as shown in FIG. 9, for example, a delay @(js-1
In order to obtain the signal VO3 of the input signal ■i, three stages of flip-flops are used in the same way to obtain the signal VO3 of the input signal ■i.
In order to obtain the signal Vos of js jo), it is necessary to use five stages of flip 70 tubes.

Further, in the conventional circuit, when following an input signal and removing certain frequency components, it is necessary to vary the delay a in the delay circuit 2, which has the problem of cumbersome operation.

(Means for solving problems) FIG. 1 shows a basic block diagram of the circuit of the present invention.

In the figure, 25 is a constant value generating circuit that generates a constant value αi corresponding to a predetermined delay amount di, and 21 is a constant value generating circuit that adds a constant value αi to the input signal Vi(t) every 172 cycles of the input signal Vi(t). An adder circuit, 26, 27 is an amplitude limiting circuit that limits the amplitude of the output signal of the adder circuit 21 by a predetermined level lower than the maximum value and a level that is a predetermined level higher than the minimum value, respectively, to a flat level; 28 is an amplitude limiter; Circuit (26,
27) is a DC level adjustment circuit that lowers the DC level of the output signal of the filter means (10, 1).
1, 12>, and 17 is a calculation means for calculating the output of the filter means and the input signal to extract a signal of a predetermined frequency component from the input signal.

[Operation] By adding a constant value αi to the input signal Vi (t), limiting the amplitude of its maximum value and minimum value, and lowering its DC level, obtain signals delayed by a different predetermined delay a. A signal with a predetermined frequency component is obtained by connecting a plurality of filter circuits in parallel and calculating the outputs of these circuits and input signals.

〔Example〕

FIG. 2 shows a concrete block diagram of an embodiment of the circuit of the present invention. Hereinafter, the signals to be handled will be, for example, digital signals, but since it is difficult to understand the waveforms of digital signals as they are, analog signal waveforms will be used for explanation.

In the same figure, reference numerals 10, 11, and 12 are filter circuits each having different frequency characteristics, and as shown in FIG.
It is composed of a DC level adjustment circuit 28, and is provided in parallel to the input. Input and each filter circuit 1
The output of 0.11.12 is supplied to the arithmetic circuit 17, where it is subjected to various arithmetic operations, unnecessary frequency components are removed, and then extracted.

Here, the filter circuit 10.11.degree. 12 in FIG. 2 will be explained. FIG. 3 shows a circuit diagram for one of these filter circuits. For example, a triangular wave input signal entered into the terminal 20 @
QO-07<solid line in 121 (D)) is supplied to the addition circuit 21, while addition timing signal CAR (FIG. 4 (A)) inputted to the terminal 22 is supplied to the constant value generation circuit 25. Ru.

The addition timing signal @CAR has a timing corresponding to 1/2 period of the input signal, and is supplied to the constant value generation circuit 25, where the constant value αi is obtained only during the 1-level period of the signal CAR. The constant value αi is supplied to the adder circuit 21. In the adder circuit 21, the input signal QO-07 is applied only during the H level period according to the timing of the addition timing signal CAH.
A constant value αi is added to , and the signals shown by the solid line and the two-dot chain line shown in FIG. 4(B) are extracted.

This signal is amplitude-limited by the next maximum value amplitude limiting circuit 26 by a predetermined level below the maximum value (the part indicated by the chain double-dashed line in FIG. 4(B)), and is made into a flat level. B)
The signal shown in the solid line is the only signal shown. Furthermore, this signal is supplied to a minimum amplitude limiting circuit 27 including a comparator 27a, where it is compared with the level shown by the dashed line in FIG. The amplitude is limited to a flat level, as shown in Figure 4 (
The signal 5o-87 is indicated by the solid line in C).

Signal 5o-87 is a subtraction circuit (DC level adjustment circuit) 28
The direct current level is lowered to produce signals DQO to DQ7 shown in FIG. 4(D), which are taken out from terminal 29. The amount of delay of the output signal DQO-DQ7 with respect to the input signal QO-Q7 corresponds to the constant value di, and a desired amount of delay can be obtained by appropriately selecting the constant value αi.

In this way, the triangular wave input signals QO to Q7 (Fig. 4 (D
), a constant value αi is added every 1/2 cycle, and the maximum and minimum amplitudes are limited, and the DC level is shifted to remove unnecessary frequency components. The signal has a desired frequency.

In this case, when the constant value α is kept constant, if input signals of different frequencies come in as shown in FIGS. 7 and 8, the delay m will vary accordingly, and the frequency to be removed will be It is possible to obtain an output signal that follows the frequency of the signal and has frequency characteristics according to the frequency characteristics of the input signal. Therefore, a predetermined frequency signal can be obtained without requiring any operations such as changing the number of stages of a shift register or the clock frequency.

Returning to the block diagram shown in FIG. Filter circuit 10.1
Each delay ff11/2 (dx +1) of 1.12.

1/2 (dy +1) and 1/2 Cdz +1) are generated by respectively setting the constant value αi of the constant value generating circuit 25 in FIG. In this case, the signal CAR in FIG. 3 is common, and various αi can be obtained by simply changing the combination of H and L levels of the input terminals of each AND gate of the constant value generating circuit 25. The input signal signal b (FIG. 5), which is delayed by the filter circuit 12 ff11/2 (d
z+1) to form signal C (FIG. 5).

The signals a and b are added to the adder 3o of the arithmetic circuit 17 to form the signal d (FIG. 5), while the input signal X is inverted by the inverter 31 of the arithmetic circuit 17 and sent to the adder 32. signal d
is added to form a signal e (FIG. 5). The signal e and the signal C are supplied to an adder 33 and a 1/2 subtracter 34, where they are operated and converted into a signal Y (FIG. 5), which is output.

Due to its nature, the triangular wave input signal @X is generally X(t)
=A+ CO3ωo t +A3 CO33(c)
o j+As cos5ωot+... Contains harmonic components of odd number times. In the present invention, the input signal @
Harmonics, which are unnecessary frequency components, are removed from X, and an approximately sinusoidal output signal Y is obtained.

In this case, each delay m of the filter circuits 10, 11, and 12 is varied according to the frequency of the input signal, the frequency to be removed follows the frequency of the input signal, and the output has frequency characteristics according to the frequency characteristics of the input signal. I can get a signal.

Note that the number of stages of the filter circuit is not limited to three stages as in the above embodiment, but is appropriately set depending on the frequency characteristics to be obtained.

〔Effect of the invention〕

According to the circuit of the present invention, a signal of a predetermined frequency component can be obtained by simply connecting in parallel a filter circuit that adds an input signal to a constant value, then limits the amplitude of the maximum and minimum values, and lowers the DC level. As a result, the circuit can be configured more easily and inexpensively than conventional circuits that use ultrasonic delay lines and shift registers as filter circuits, and in particular, the frequency characteristics that follow the frequency of the input signal can be improved. Since it is possible to obtain a signal with a predetermined frequency, for example, it is possible to obtain a predetermined frequency signal without requiring any operations such as changing the number of stages of a shift register or changing the operating frequency.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the circuit of the present invention, FIG. 2 is a concrete block diagram of the circuit of the present invention, FIG. 3 is a circuit diagram of a main part of an embodiment of the circuit of the present invention, and FIG. 5 is a timing chart of signals of the circuit shown in FIG. 2, FIG. 6 is a block diagram of a conventional circuit, and FIGS. FIG. 9 is a diagram explaining the number of stages of the shift register. In the figure, 10.11.12 is a filter circuit, 17 is an arithmetic circuit, 20 is a signal input terminal, 21.30.32.33 is an addition circuit, 22 is an addition timing signal input terminal, 25 is a constant value generation circuit, 26 27 is a maximum amplitude limiting circuit, 27 is a minimum amplitude limiting circuit, 28 is a subtraction circuit (DC level adjustment circuit), 29 is an output terminal, 31 is an inverter, and 34 is a 1/2 attenuation mixer. The original Katta Shi principle 7072 field Fig. 1 (A) CAR Fig. 3 1 = Neo Kaidai 4 Supper No. Tahari” + P4 Fig. 4

Claims (1)

[Claims] In a signal processing circuit having a function of filtering a signal of a predetermined frequency component from an input signal (Vi(t)), a predetermined amount of delay (
a constant value generating circuit (25) that generates a constant value (αi) corresponding to di), and 1/2 of the input signal (Vi(t)).
The input signal (Vi(t)) is set to the constant value (α
an adder circuit (21) that adds i);
) amplitude limiting circuits (26, 27) that limit the amplitude of the output signal of the output signal at a level that is a predetermined level lower than the maximum value and a level that is a predetermined level increase from the minimum value, respectively, to a flat level;
A plurality of filter circuits (10, 11, 12) connected in parallel to the input are provided with a DC level adjustment circuit (28) that lowers the DC level of the output signal of the amplitude limiting circuit (26, 27). ), the output of the filter means (10, 11, 12) and the input signal (Vi(t)) are calculated to obtain the input signal (Vi(t)).
arithmetic means (1) for extracting a signal of a predetermined frequency component from
7) A signal processing circuit characterized by the following.