JPH0322092B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The present invention provides a signal processing circuit that removes unnecessary frequency components from an input signal to obtain a signal of a desired frequency. In order to solve the problem of conventional circuits in which the amount of delay must be changed when removing a certain frequency component, multiple filter circuits are commonly connected in parallel to the input, and this filter circuit is connected to the input signal at a constant rate. a signal level between the maximum value of the output of the adder circuit and the maximum value of the input signal level, and a signal level between the minimum value of the output signal and the input signal level at the minimum value of the output signal level. The structure consists of a circuit that limits the amplitude of the signal level between the two, and a circuit that changes the output level of the amplitude limiting circuit by an amount corresponding to the amount of delay. The present invention is designed to obtain a signal of a desired frequency component without requiring a special configuration.

[Industrial application field]

The present invention relates to a signal processing circuit, and particularly to a signal processing circuit that extracts a signal of a desired frequency component from an input signal, and is applied to digital filters, analog filters, and the like.

[Prior Art] Known conventional circuits for obtaining delayed signals include, for example, analog signal processing circuits using ultrasonic delay lines and the like, and digital signal processing circuits using flip-flop shift registers and the like.

FIG. 6 shows a block diagram of a conventional circuit for removing a certain frequency component from an input signal, and FIG. 7 or 8 shows a signal timing chart of the circuit shown in FIG. 6.

Hereinafter, the signals to be handled will be, for example, digital signals, but since it is difficult to understand the waveforms of digital signals as they are, analog signal waveforms will be used for explanation.

In Figure 6, the input signal coming into terminal 1
V ₁ (t) (or V ₂ (t)) is delayed by a delay amount d ₁ (or d ₂ ) in a delay circuit 2 such as a shift register, and is converted into a signal x ₁ (or x ₁ '), which is then sent to an adder. 3 to form a signal x ₂ (or x ₂ '). The signal x ₂ (or x ₂ ′) is attenuated to 1/2 in level by the 1/2 attenuator 4 to become a signal V ₀₁ (t) (or V ₀₂ (t)), which is taken out through the terminal 5.

Here, the input signal V ₁ (t) or V ₂ (t) is Vi
(t), output signal V ₀₁ (t) or V ₀₂ (t), V ₀ (t),
If the delay amount d ₁ or D ₂ is di, then V ₀ (t) = 1/2 [Vi (t-di) + Vi (t)] (1) holds true for the input signal Vi (t) in the above formula. Delayed signal Vi
(t-di) as Vi(t-di)≡Vi(t)±αi (2) However, if we set αi=2vi・di/Ti and substitute equation (2) into equation (1), we get V ₀ ( t)=1/2 [Vi(t)±αi+Vi(t)] =Vi(t)±Ci However, Ci=(1/2)αi. Here, vi is the peak value of the input signal, and Ti is the period of the input signal.

[Problem that the invention seeks to solve]

The conventional circuit is constructed using an ultrasonic delay line or a shift register as the delay circuit 2 shown in FIG. 6, but there is a problem that the circuit is large and cannot be constructed compactly. In a conventional circuit using a shift register, the input signal is
For example, to obtain a signal V ₀₃ with a delay amount (t ₃ - t ₀ ) for Vi, three stages of flip-flops are used, and similarly,
In order to obtain the signal V ₀₅ with a delay amount (t ₅ -t ₀ ) for the input signal Vi, it is necessary to use five stages of flip-flops.

Further, in the conventional circuit, when following an input signal and removing certain frequency components, it is necessary to vary the amount of delay in the delay circuit 2, which has the problem of cumbersome operation.

[Means for solving problems]

FIG. 1 shows a basic block diagram of the circuit according to the invention.
In the figure, 25 is a constant value αi corresponding to the predetermined delay amount di.
21 is an input signal Vi
A constant value αi is applied to the input signal Vi(t) every 1/2 period of (t).
26 and 27 are adder circuits 21
An amplitude limiting circuit that limits the amplitude of the input signal level between the maximum value of the output signal level and the maximum value of the input signal level and between the minimum value of the output signal and the minimum value of the output signal level in the output signal of the output signal. , 28 is a DC level adjustment circuit that changes the DC level of the output signal of the amplitude limiting circuits 26 and 27 by an amount corresponding to the amount of delay, and a plurality of filter circuits constituted by these are connected in parallel to the input. and filter means 10, 11, 12, 1
Reference numeral 7 denotes a calculation means for calculating the output of the filter means and the output signal to extract a signal of a predetermined frequency component from the input signal.

[Effect]

By adding a constant value αi to the input signal Vi(t), limiting the amplitude of the maximum value and the minimum value, and lowering the DC level, a filter circuit obtains signals delayed by different predetermined delay amounts. A plurality of circuits are connected in parallel and a signal of a predetermined frequency component is obtained by calculating each output of these circuits and an input signal.

〔Example〕

FIG. 2 shows a concrete block diagram of one embodiment of the circuit of the present invention. Hereinafter, the signals to be handled will be, for example, digital signals, but since it is difficult to understand the waveforms of digital signals as they are, analog signal waveforms will be used for explanation.
In the figure, reference numerals 10, 11, and 12 are filter circuits each having different frequency characteristics, and as shown in FIG. It is configured in parallel with the input. Input and each filter circuit 10, 11, 12
The output is supplied to an arithmetic circuit 17, where it is subjected to various calculations, unnecessary frequency components are removed, and then extracted.

Here, in FIG. 2, filter circuits 10, 11,
12 will be explained. FIG. 3 shows a circuit diagram for one of these filter circuits. For example, triangular wave input signals Q0 to Q7 (solid lines in FIG. 4D) inputted to the terminal 20 are supplied to the adder circuit 21, while
Addition timing signal CAR entered (Fig. 4A)
is supplied to the constant value generation circuit 25.

The addition timing signal CAR has a timing corresponding to 1/2 period of the input signal, and is connected to the constant value generation circuit 25.
Here, a constant value αi is obtained only during the H level period of the signal CAR. The constant value αi is the adder circuit 21
is supplied to In the adder circuit 21, a constant value αi is added to the input signals Q0 to Q7 only during the H level period according to the timing of the addition timing signal CAR, and the signals shown by the solid line and the two-dot chain line shown in FIG. 4B are taken out.

This signal is passed to the next maximum value amplitude limiting circuit 26 by a predetermined level below the maximum value (in FIG. 4B,
(portion indicated by the two-dot chain line) The amplitude is limited to a flat level, resulting in only the solid line signal shown in FIG. 4B. Furthermore, this signal is supplied to a minimum amplitude limiting circuit 27 including a comparator 27a, where it is compared with the level shown by the dashed line in FIG. The signal level is set to a flat level, and the signals S0 to S7 shown by solid lines in FIG. 4C are obtained.

The signals S0 to S7 have their DC levels lowered by a subtraction circuit (DC level adjustment circuit) 28 to become signals DQ0 to DQ7 shown in FIG. The amount of delay of the output signals DQ0 to DQ7 with respect to the input signals Q0 to Q7 corresponds to the constant value di, and a desired amount of delay can be obtained by appropriately selecting the constant value αi.

In this way, the triangular wave input signals Q0 to Q7 (solid line in Figure 4 D) have a constant value αi added to them every 1/2 cycle, and their maximum and minimum amplitudes are limited, and the DC By shifting the level, unnecessary frequency components are removed and a signal of a desired frequency is obtained.

In this case, when the constant value αi is kept constant, if input signals of different frequencies come in as shown in Figures 7 and 8, the amount of delay will vary accordingly, and the frequency to be removed will be the input signal. It is possible to obtain an output signal that follows the frequency of the input signal and has frequency characteristics corresponding to the frequency characteristics of the input signal. Therefore, a predetermined frequency signal can be obtained without requiring any operations such as changing the number of stages of a shift register or the clock frequency.

Returning to the block diagram shown in FIG. Delay amount 1/2 (dx+1) of filter circuits 10, 11, 12,
1/2 (dy+1) and 1/2 (dz+1) are shown in Figure 3.
It is created by setting the constant value αi of the constant value generation circuit 25, respectively. In this case, the signal CAR in FIG. 3 is common, and various αi can be obtained by simply changing the combination of H and L levels of the input terminals of each AND gate of the constant value generating circuit 25. The input signal X (Fig. 5) is delayed by 1/2 (dx+
1) and is delayed as signal a (Fig. 5),
The signal is delayed by a delay amount of 1/2 (dy+1) in the filter circuit 11 and becomes a signal b (Fig. 5), and the signal is delayed by a delay amount of 1/2 (dz+1) in the filter circuit 12 and becomes a signal c (Fig. 5). be done.

The signals a and b are added in the adder 30 of the arithmetic circuit 17 to form the signal d (FIG. 5), while the input signal X is inverted in the inverter 31 of the arithmetic circuit 17.
The adder 32 adds the signal d to the signal e (fifth
Figure). The signal e and the signal c are sent to an adder 33,
The signal Y is supplied to the 1/2 subtracter 34, where it is calculated and output as a signal Y (FIG. 5).

_{Due to} its _nature , _the triangular wave input signal X _generally includes odd harmonic components as follows _: In the present invention, harmonics, which are unnecessary frequency components, are removed from the input signal X, and an output signal Y having a substantially sinusoidal waveform is obtained.
In this case, the amount of delay of each of the filter circuits 10, 11, and 12 is varied according to the frequency of the input signal, the frequency to be removed follows the frequency of the input signal, and the output has frequency characteristics according to the frequency characteristics of the input signal. I can get a signal.

Note that the number of stages of the filter circuit is not limited to three stages as in the above embodiment, but is appropriately set depending on the frequency characteristics to be obtained.

〔Effect of the invention〕

According to the circuit of the present invention, a signal of a predetermined frequency component can be obtained by simply connecting in parallel a filter circuit that adds an input signal to a constant value, then limits the amplitude of the maximum and minimum values, and lowers the DC level. As a result, the circuit can be constructed more easily and inexpensively than conventional circuits using ultrasonic delay lines, shift registers, etc. as filter circuits, and in particular,
Since it is possible to obtain a signal with frequency characteristics that follow the frequency of the input signal, it is possible to obtain a predetermined frequency signal without requiring any operations such as changing the number of stages of a shift register or the clock frequency. It has characteristics.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the circuit of the present invention, FIG. 2 is a specific block diagram of the circuit of the present invention, FIG. 3 is a circuit diagram of the main part of an embodiment of the circuit of the present invention, and FIG.
Timing chart of signals of the circuit shown in figure 5
The figures are a timing chart of the signals in the block diagram shown in Fig. 2, Fig. 6 is a block diagram of the conventional circuit, and Fig. 7 is a timing chart of the signals in the block diagram shown in Fig. 2.
8 and 8 are timing charts of signals in the circuit shown in FIG. 6, and FIG. 9 is a diagram for explaining the number of stages of the shift register. In the figure, 10, 11, 12 are filter circuits, 17 is an arithmetic circuit, 20 is a signal input terminal, 2
1, 30, 32, 33 are adder circuits, 22 is an addition timing signal input terminal, 25 is a constant value generation circuit,
26 is a maximum value amplitude limiting circuit, 27 is a minimum value amplitude limiting circuit, 28 is a subtraction circuit (DC level adjustment circuit),
29 is an output terminal, 31 is an inverter, and 34 is a 1/2 attenuator.

Claims (1)

[Claims] 1. A plurality of filter means 10, 11, 12 commonly connected in parallel to the input, and calculating the outputs of the filter means 10, 11, 12 and the input signal Vi(t). A signal processing circuit comprising a calculation means 17 for extracting a signal of a predetermined frequency component from the input signal Vi(t), wherein the filter means generates a constant value (αi) corresponding to a predetermined amount of delay (di). Constant value generation circuit 15
and an adder circuit 21 that adds the constant value (αi) to the input signal Vi(t) every 1/2 period of the input signal Vi(t), and among the output signals of the adder circuit 21, the output signal The signal level between the maximum level and the maximum value of the input signal Vi(t) level, and the signal level between the minimum value of the output signal and the input signal level at the minimum value of the output signal level. Amplitude limiting circuits 16 and 17 that limit the amplitude, respectively, and a DC level adjustment circuit 18 that changes the DC level of the output signal of the amplitude limiting circuits 16 and 17 by an amount corresponding to the delay amount (di). Characteristic signal processing circuit.