JPS6181021A - Noise eliminating circuit - Google Patents

Noise eliminating circuit

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Publication number
JPS6181021A
JPS6181021A JP59203686A JP20368684A JPS6181021A JP S6181021 A JPS6181021 A JP S6181021A JP 59203686 A JP59203686 A JP 59203686A JP 20368684 A JP20368684 A JP 20368684A JP S6181021 A JPS6181021 A JP S6181021A
Authority
JP
Japan
Prior art keywords
circuit
noise
pulse
time
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59203686A
Other languages
Japanese (ja)
Other versions
JPH0441845B2 (en
Inventor
Osamu Kawabata
理 川畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP59203686A priority Critical patent/JPS6181021A/en
Priority to US06/780,170 priority patent/US4710705A/en
Priority to DE8585306863T priority patent/DE3569988D1/en
Priority to EP85306863A priority patent/EP0180322B1/en
Publication of JPS6181021A publication Critical patent/JPS6181021A/en
Publication of JPH0441845B2 publication Critical patent/JPH0441845B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To attenuate or eliminate a single shot or periodical noise which has a rise time and a fall time longer than the duration of a pulse signal to be measure, by converting the pulse signal to be measured to a three-pulse train including an input pulse and two delay pulses and not only reducing the noise in accordance with a ratio of the rise time and the fall time to a delay time but also converting the noise to a single pulse having a short time width and allowing this pulse to pass a multiplying circuit. CONSTITUTION:In case of the noise whose rise time taun is longer than the delay time, the first phase shift subtracting means 11 delays one input signal of a subtracting circuit 13 by a time Td to reduce the noise, and the second phase shift subtracting means 14 delays one input signal of a subtracting circuit 16 by the time Td furthermore to separate the noise to plural single pulses, and a noise eliminating circuit 17 controls overlap of single pulses to make the multiplication result of zero, and thus, the noise is reduced considerably as the whole.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は電子計測器、電子制御装置等において単発性の
被計測パルス信号に含まれる立上υ、立下り時間が被計
測パルス信号の持続時間より長い単発性あるい−は周期
性ノイズを低減あるいは除去するためのノイズ除去回路
に関する。
[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to the rise and fall times included in a single pulse signal to be measured in electronic measuring instruments, electronic control devices, etc. The present invention relates to a noise removal circuit for reducing or removing single-shot or periodic noise that is longer than time.

〔従来技術とその問題点〕[Prior art and its problems]

被検体である電気機器や機械装置側から電子計測器等に
入力される被計測パルス信号の波形や波高値あるいは発
生頻度等を計測あるいは観測することにより被検体の特
性を評価しようとする場合、被検体がアンテナとなって
計測回路に侵入する放送電波等の周期的ノイズ、おるい
は電力系統等を介して測定回路に侵入する開閉ノイズ、
放電ノイズ等の単発性ノイズ等のレベルが高いと、測定
回路等のS/N比が低下して被検体の特性の評価精度が
低下する。したがって電子計測器等においてはノイズ除
去が重要な課題になっている。
When attempting to evaluate the characteristics of a test object by measuring or observing the waveform, peak value, or frequency of occurrence of a pulse signal to be measured that is input to an electronic measuring instrument from the electrical equipment or mechanical device being tested, Periodic noise such as broadcast radio waves that intrude into the measurement circuit by using the object as an antenna, or switching noise that intrudes into the measurement circuit via the power system, etc.
When the level of single-shot noise such as discharge noise is high, the S/N ratio of the measurement circuit and the like decreases, resulting in a decrease in the accuracy of evaluating the characteristics of the object. Therefore, noise removal has become an important issue in electronic measuring instruments and the like.

ノイズ除去回路としては、従来被計測パルス信号に含ま
れる主要周波数成分を通過帯域とするフィルタを用いる
のが一般的であるが、S/N比を向上させるために通過
帯域幅を狭くすればパルス信号波形が変歪まだは振動し
、通過帯域幅をひろげればパルス信号の主要周波数成分
に近い波形のノイズに対するS/N比が低下するという
問題があり、満足しうるノイズ除去性能とパルス信号の
原波形維持性能とを併せ持つノイズ除去回路が得られな
いのが実情であった。
Conventionally, as a noise removal circuit, it is common to use a filter whose passband is the main frequency component included in the pulse signal under measurement. There is a problem in that the signal waveform is distorted and oscillates, and if the passband width is widened, the S/N ratio for noise with a waveform close to the main frequency component of the pulse signal decreases. The reality is that it has not been possible to obtain a noise removal circuit that has the ability to maintain the original waveform.

第6図は改良された従来のノイズ除去回路の構は昭和5
9年電気学会全国大会論文、NCL1283参照)。図
において1は被検体である箪カケープ・−ル、2は電カ
ケープル1に試験電圧を印加するた1   めの端末ブ
ッシング、6は部分放電パルス検出用の結合コンデンサ
、4は検出インピーダンス、5は遅延線6ならびに加算
回路7からなるノイズ除去回路、8は部分放電パルスの
増幅回路である。
Figure 6 shows the structure of an improved conventional noise removal circuit developed in Showa 5.
(Refer to 1999 National Conference of the Institute of Electrical Engineers of Japan Papers, NCL1283). In the figure, 1 is the electrical cable to be tested, 2 is the terminal bushing for applying the test voltage to the electrical cable 1, 6 is the coupling capacitor for partial discharge pulse detection, 4 is the detection impedance, and 5 is the terminal bushing for applying the test voltage to the electrical cable 1. A noise removal circuit includes a delay line 6 and an adder circuit 7, and 8 is a partial discharge pulse amplification circuit.

第7図は第6図のノイズ除去回路の作用を説明するだめ
の信号波形図で、図中w4.w、5.w7はそれぞれ入
力回路10の出力信号波形(検出インピーダンス4の端
子電圧)、遅延線乙の出力信号波形、加算回路7の出力
信号波形を示すものである。図において入力信号W4に
は被計測信号である部分放電パルスP1と周期τなる周
期的ノイズN1とが混在している。遅延線6は周期的ノ
イズN1の部分の一周期(τ/2)に相当する遅延時間
を有するよう形成されることにより、その出力波形W6
は、ノイズN堂、放電パルスP、ともに入力信号N1.
Plよりそれぞれτ/2時間遅れて出力される。その結
果、加算回路7に入力される入力信号w4.w6のうち
ノイズN1.N、は互いに逆位相となり、両者が加算さ
れることによって消去されるが、放電パルスP□、P!
はそのま\出力され、増幅回路8にはノイズ除去回路5
を通ることによって2個の信号パルスp1.p、に増加
した放電パルス列が入力され、たとえば出力端子9に接
続された観測装置等で観測される。
FIG. 7 is a signal waveform diagram for explaining the operation of the noise removal circuit shown in FIG. 6. In the figure, w4. w, 5. w7 indicates the output signal waveform of the input circuit 10 (terminal voltage of the detection impedance 4), the output signal waveform of the delay line O, and the output signal waveform of the addition circuit 7, respectively. In the figure, the input signal W4 includes a partial discharge pulse P1, which is a signal to be measured, and a periodic noise N1 having a period τ. The delay line 6 is formed to have a delay time corresponding to one period (τ/2) of the periodic noise N1, so that its output waveform W6
Both the noise Ndo and the discharge pulse P are the input signal N1.
Each signal is output with a delay of τ/2 hours from Pl. As a result, the input signal w4. input to the adder circuit 7. Noise N1 of w6. N, have opposite phases to each other and are erased by adding them together, but the discharge pulses P□, P!
is output as is, and the amplifier circuit 8 is connected to the noise removal circuit 5.
By passing two signal pulses p1. The increased discharge pulse train is input to p, and is observed by, for example, an observation device connected to the output terminal 9.

上述のように第6図のように構成されたノイズ除去回路
においては遅延線6によシ周期的ノイズを部分の一周期
分遅延させて入力ノイズと逆位相の遅延パルスを作り、
両者を加算することによυ消去するようにしているため
に、遅延線乙の遅延時間を周期的ノイズの周期に一致さ
せるよう調整する必要があるばか)か、複数の周期性ノ
イズがある場合には複数組のノイズ除去回路を必要とす
るという問題点がある。またノイズが放電パルスと同様
な単発的ノイズである場合には、ノイズのパルス数を2
倍に増してしまうという問題点がある。
As mentioned above, in the noise removal circuit configured as shown in FIG. 6, the periodic noise is delayed by one period of the part by the delay line 6 to create a delayed pulse having the opposite phase to the input noise.
Because we are trying to eliminate υ by adding both, we need to adjust the delay time of the delay line B to match the period of the periodic noise) or if there are multiple periodic noises. This method has a problem in that it requires multiple sets of noise removal circuits. In addition, if the noise is a one-shot noise similar to a discharge pulse, the number of noise pulses should be increased by 2.
The problem is that it doubles.

〔発明の目的〕[Purpose of the invention]

本発明は前述の状況に鑑みてなされたもので、被計測パ
ルス信号を変歪させずに、被計測パルス信号の持続時間
に比べて長い立上り、立下シ時間を有する単発性あるい
は周期性ノイズを減衰または除去できるノイズ除去回路
を提供することを目的とする。
The present invention has been made in view of the above-mentioned situation, and it is possible to eliminate one-shot or periodic noise that has a long rise and fall time compared to the duration of the pulse signal to be measured without distorting the pulse signal to be measured. The purpose of the present invention is to provide a noise removal circuit that can attenuate or remove noise.

〔発明の要点〕[Key points of the invention]

本発明は、波高値の変動等にともなう持続時間の上限値
を考慮した被計測パルス信号の持続時間と同等またはそ
れ以上の遅延時間にあらかじめ設定された遅延回路およ
びこの遅延回路の入力信号。
The present invention relates to a delay circuit that is preset to a delay time equal to or longer than the duration of a pulse signal to be measured, taking into account the upper limit of duration due to fluctuations in peak value, etc., and an input signal to this delay circuit.

出力信号を入力信号とする減算回路複数組たとえば2組
を互いに縦続接続してたとえば第1および第2の移相減
算手段を構成することにより、被計測パルス信号を入力
パルスと2個の遅延パルスとを含む3個のパルス列に変
換するとともにノイズをその立上り、立下り時間と遅延
時間の比に対応して低減かつ時間幅の短かい単一パルス
に変換し前記移相減算手段の出力側に前記移相減算手段
の総遅延時間と等しい遅延時間を有する遅延回路とこの
遅延回路の入力信号、出力信号を入力信号とする掛算回
路とからなるノイズ消去手段を設けることにより前記3
個のパルス列全体をさらに前記総遅延時間だけ遅延させ
て両パルス列それぞれ5個のパルス信号のうち一つづつ
のみが同一時刻に重なるようにして両者を掛算すること
によシ同一時刻に重なったパルスのみを残して他のパル
スを消去するとともに、移相減算手段によシ時間幅が短
縮されて単一パルス状となったノイズパルスと重なりを
制御された遅延パルスとを掛算することにより消去し、
前記同一時刻に重なった被計測パルス信号のみを原波形
に相似なパルス信号として出力するようにしたものであ
る。
By connecting a plurality of subtraction circuits, for example, two sets, in cascade with each other to constitute, for example, first and second phase shift subtraction means, which take an output signal as an input signal, the pulse signal to be measured is divided into an input pulse and two delayed pulses. and converts the noise into a single pulse having a short time width and reducing the noise corresponding to the ratio of the rise time, fall time and delay time, and outputs the pulse train to the output side of the phase shift subtraction means. By providing a noise canceling means comprising a delay circuit having a delay time equal to the total delay time of the phase shift subtracting means and a multiplication circuit whose input signals are the input signal and output signal of this delay circuit,
The entire pulse train is further delayed by the total delay time so that only one of the five pulse signals in each pulse train overlaps at the same time, and by multiplying the two, the pulses that overlap at the same time are obtained. The noise pulse, whose time width has been shortened by the phase shift subtraction means and becomes a single pulse, is multiplied by a delayed pulse whose overlap is controlled. ,
Only the measured pulse signals that overlap at the same time are output as pulse signals similar to the original waveform.

〔発明の実施例〕[Embodiments of the invention]

以下本発明を実施例に基づいて説明する。 The present invention will be explained below based on examples.

第1図は本発明の実施例を示すノイズ除去回路の偏成を
示すブロック図である。図において、10はインピーダ
ンス底台回路等の入力回路で、ノイズを含む被計測パル
ス信号が原波形に近いアナログ信号として出力される。
FIG. 1 is a block diagram showing the configuration of a noise removal circuit according to an embodiment of the present invention. In the figure, reference numeral 10 denotes an input circuit such as an impedance base circuit, from which a pulse signal to be measured containing noise is output as an analog signal close to the original waveform.

11は第1の移相減算手段、14は第1の移相減算手段
に縦続接続された第2の移相減算手段で、それぞれ被計
測パルス信号の持続時間Wpに等しい遅延時間Taにあ
らかじめ設定された遅延綜、ディジタル式遅延回路等か
らなる遅延回路12あるいは15と、遅延回路12ある
いは15の入力信号および出力信号を入力信号とする減
算回路13あるいは16とで構成されている。また17
は第2の移相減算手段14の出力信号を入力信号とする
ノイズ消去手段で、第1.第2の移相減算手段の総遅延
時間いわゆる2T(lと等しい遅延時間にあらかじめ設
定された遅延回路18と、この遅延回路の入出力信号を
入力信号とする掛算回路19とで構成されており、その
出力側には開平回路、増幅回路、減衰回路。
11 is a first phase shift subtraction means, and 14 is a second phase shift subtraction means connected in cascade to the first phase shift subtraction means, each of which is set in advance to a delay time Ta equal to the duration Wp of the pulse signal to be measured. The delay circuit 12 or 15 includes a delay helix, a digital delay circuit, etc., and a subtraction circuit 13 or 16, which receives the input signal and output signal of the delay circuit 12 or 15 as input signals. Also 17
1. is a noise canceling means which uses the output signal of the second phase shift subtraction means 14 as an input signal; It consists of a delay circuit 18 which is preset to a delay time equal to the total delay time of the second phase shift subtraction means, so-called 2T (l), and a multiplication circuit 19 whose input signal is the input/output signal of this delay circuit. , and its output side includes a square root circuit, an amplification circuit, and an attenuation circuit.

インピーダンス整合回路等必要に応じて選択される出力
回路20が設けられている。
An output circuit 20 such as an impedance matching circuit is provided, which is selected as necessary.

第2図は第1図のように構成されたノイズ除去回路の作
用を説明するための信号波形図で、入力信号として持続
時間(パルス幅) Wpが5On8の台形波からなる被
計測パルス信号P1゜と、立上り、立下シ時間τ九がパ
ルス幅Wpの12倍すなわち600nSの台形波からな
る単発性のノイズN11lとを第1図のノイズ除去回路
に注入するとともに、移相減算手段等の遅延回路には遅
延時間Taが被計測パルス信号P1゜のパルス幅と等し
い遅延線(昭和電線製、商品名シングル・イン・ライン
型遅延%9AT型)を、減算回路には広帯域オペアンプ
(米国、oei社委、型番9826)を、掛算回路には
広帯域リニア乗算器(米国、アナログ・デバイセズ社製
、型番AD539)をそれぞれ用いてノイズ除去回路を
構成することによって得られた信号波形を示しだもので
ある。ただし上述の回路構成部品はパルス幅Wpが50
n8と短かい被計測パルス信号の原波形を維持するに好
適な回路(h成部品の一例を示したもので、Wp、τd
等が大幅に異なる場合にはパルス(M号波形の原波形を
維持するに好適な構成部品を選択すべきことはいうまで
もないことである。図において、Wl。は入力回路の出
力信号波形であり、Ploは時刻t、に出力されたパル
ス幅Wpなる台形状の被計測パルス信号、N1゜は時刻
toに入力回路から出力された立上り、立下り時間τ”
=12Wpなる台形状の単発性ノイズパルスで、立下り
部分を省略して示したものである。WISは第1の8相
誠算十段11における遅延回路12の出力信号波形であ
り、ノイズN□、はto0時刻p’ra==wp時間だ
け遅れて、またパルス信号putはt1時刻よシWp時
間だけ遅れてそれぞれ原波形に近い形で出力される。W
l、はWl。およびWSSを入力とする減算回路16の
出力信号で、パルス信号Pl婁についてはWp待時間れ
たPl・とPII とを減算することにより、t1時刻
に立上がるPl。とt1時刻からWp時間遅れて負側に
立上がるPloの遅延パルスFilとから力る正負一対
のパルス列pHが出力される。またノイズパルスN1m
については、 to0時刻ら遅延時間Wpで立上がり、
Nl11の立上がシ時間τ几の終シに相当する時刻t1
からWp待時間立下がる台形状パルスとなり、ノイズN
18の波高値は入力ノイズパルスNIOのほぼ1/12
に低減されるとともに、そのパルス幅もN1oの立上が
り、立下がり時間τ九に遅延時間Wpを加えた時間に短
縮される。
FIG. 2 is a signal waveform diagram for explaining the operation of the noise removal circuit configured as shown in FIG.゜ and a single-shot noise N11l consisting of a trapezoidal wave whose rise and fall times τ9 are 12 times the pulse width Wp, that is, 600 nS, are injected into the noise removal circuit of FIG. 1, and the phase shift subtraction means etc. The delay circuit uses a delay line whose delay time Ta is equal to the pulse width of the pulse signal P1° to be measured (manufactured by Showa Cable, product name: single-in-line delay %9AT type), and the subtraction circuit uses a wideband operational amplifier (made in the United States, This figure shows the signal waveform obtained by configuring a noise removal circuit using a noise removal circuit using a wideband linear multiplier (manufactured by Analog Devices, Inc., USA, model number AD539) for the multiplication circuit. It is. However, the above circuit components have a pulse width Wp of 50
This circuit is suitable for maintaining the original waveform of the pulse signal to be measured as short as n8.
It goes without saying that components suitable for maintaining the original waveform of the pulse (M waveform) should be selected when the waveforms, etc. are significantly different. In the figure, Wl. is the output signal waveform of the input circuit. where Plo is a trapezoidal measured pulse signal with a pulse width Wp output at time t, and N1° is the rise and fall time τ output from the input circuit at time to.
This is a trapezoidal single-shot noise pulse of =12Wp, with the falling part omitted. WIS is the output signal waveform of the delay circuit 12 in the first 8-phase arithmetic stage 11, the noise N□ is delayed by the to0 time p'ra==wp time, and the pulse signal put is delayed by the time p'ra==wp from the time t1. Each waveform is output in a form close to the original waveform with a delay of Wp time. W
l, is Wl. With respect to the pulse signal Pl, Pl rises at time t1 by subtracting Pl· and PII, which have a waiting time of Wp, from the output signal of the subtraction circuit 16 which receives the pulse signal Pl and WSS as inputs. A pair of positive and negative pulse trains pH are output from the delay pulse Fil of Plo which rises to the negative side with a delay of Wp time from time t1. Also noise pulse N1m
For, it rises with delay time Wp from time to0,
Time t1 when the rise of Nl11 corresponds to the end of time τ
It becomes a trapezoidal pulse falling from Wp waiting time, and the noise N
The peak value of 18 is approximately 1/12 of the input noise pulse NIO.
At the same time, the pulse width is also shortened to the time obtained by adding the delay time Wp to the rise and fall time τ9 of N1o.

WlllおよびWl6はそれぞれ第2の移相減算手段1
4における遅延回路15および減算回路16の出  □
力信号である。Wl、においてパルス信号Puおよびノ
イズパルスN15はそれぞれpHおよびNtm aTj
 = wp時間さらに遅延され、減算回路16でW□8
からWls が減算されることKよ)、Wl。K示すよ
うにt3時刻を始発点とする3個のパルス列からなるパ
ルス信号P16と、パルス幅2Wpなる二つの三角波に
変保されたノイズパルスN□6とが出力される。
Wlll and Wl6 are respectively second phase shift subtraction means 1
Outputs of delay circuit 15 and subtraction circuit 16 in 4 □
It is a force signal. Wl, the pulse signal Pu and noise pulse N15 are respectively pH and Ntm aTj
= further delayed by wp time, and W□8 in subtraction circuit 16
Wls is subtracted from K), Wl. As shown in K, a pulse signal P16 consisting of three pulse trains starting at time t3 and a noise pulse N□6 transformed into two triangular waves with a pulse width of 2 Wp are output.

Wl、およびWl。はそれぞれノイズ消去手段17の遅
延回路18および掛算回路19の出力信号でちる。パル
ス信号pxaは遅延時間Ta = 2 Wpに設定され
た遅延回M18を通ることにより2Wp時間遅れた遅延
パルス列P1.となり、P□6 + PIllそれぞれ
3個のパルス列のうちのそれぞれ1個づつのみが同時刻
に出力され、掛算回路19を通ることにより同時刻に重
なったパルスのみが2乗増幅されてPl。
Wl, and Wl. are respectively determined by the output signals of the delay circuit 18 and the multiplication circuit 19 of the noise canceling means 17. The pulse signal pxa passes through the delay circuit M18 set to a delay time Ta = 2 Wp, resulting in a delayed pulse train P1. which is delayed by 2 Wp. Then, only one of each of the three pulse trains P□6 + PIll is output at the same time, and by passing through the multiplication circuit 19, only the pulses that overlap at the same time are squared and amplified to become Pl.

が出力され、遅延回路によりそれぞれ重なりが回避され
た残りの4個のパルスは消去される。またN13より2
Wp遅延した遅延ノイズパルスIJtsはN1gとの重
なりが回避されることによシ掛算回路19涛   で消
去される。
is output, and the remaining four pulses whose overlaps are avoided by the delay circuits are eliminated. Also 2 from N13
The delayed noise pulse IJts delayed by Wp is eliminated by the multiplication circuit 19 by avoiding overlap with N1g.

IW・・は出力回路を開平回路とした場合のノイズ除去
回路の最終的な出力信号で、掛算回路19で2乗増幅さ
れたPl、を開平回路20を通すことによシ原波形に近
い波高値およびパルス形状の出力信号にもどすことがで
きる。ただし、各遅延回路の構成部品に高周波応答特性
のよいものを使用した場合においても信号の伝送に幾分
の減長をともない、また減算回路の構成部品には幾分の
増幅機能があるので、出力画Wh20はノイズ除去回路
全体の信号の増減を補正するために必要に応じて開平回
路、増幅回路、減衰回路等を選択使用することが好まし
い。
IW... is the final output signal of the noise removal circuit when the output circuit is a square root circuit. Pl squared by the multiplication circuit 19 is passed through the square root circuit 20 to produce a wave close to the original waveform. A high value and pulse shaped output signal can be returned. However, even if components with good high frequency response characteristics are used for each delay circuit, there will be some reduction in signal transmission, and the components of the subtraction circuit will have some amplification function. For the output image Wh20, it is preferable to selectively use a square root circuit, an amplification circuit, an attenuation circuit, etc. as necessary to correct the increase/decrease in the signal of the entire noise removal circuit.

第6図は第1図の実施例におけるノイズ除去回路の周期
性ノイズに対する動作を説明するだめの信号波形の概念
図であり、周期性ノイズとして立上がり、立下がり時間
τ九が被計測パルス信号のパルス幅Wpの2倍に相当す
る三角波である場合を例にして示したものである。なお
被計測パルス信号に対する動作は第2図と同様なので省
略した。
FIG. 6 is a conceptual diagram of a signal waveform to explain the operation of the noise removal circuit in the embodiment of FIG. 1 against periodic noise. The case where the waveform is a triangular wave corresponding to twice the pulse width Wp is shown as an example. Note that the operation for the pulse signal to be measured is the same as that in FIG. 2, so it is omitted.

図においてWIOは入力回路10の出力ノイズ波形、w
itは遅延時間Ta=Wpなる遅延回路12の出力波形
、Wlは減算回路16の出力波形で、遅延時間TcL 
=WpだけずれたノイズWwとWl鴬が減算されること
により、波高値が原波形W1゜の波高値のほぼ1/2に
低減された台形波に変換される。
In the figure, WIO is the output noise waveform of the input circuit 10, w
it is the output waveform of the delay circuit 12 with delay time Ta=Wp, Wl is the output waveform of the subtraction circuit 16 with delay time TcL
By subtracting the noise Ww and Wl which are shifted by =Wp, the waveform is converted into a trapezoidal wave whose peak value is reduced to approximately 1/2 of the peak value of the original waveform W1°.

Wlllは遅延時間T(L = Wpに設定された遅延
回路15の出力ノイズであり、出力ノイズW□、は時刻
Toに対して2’ra=2wp時間位相が遅れる。Wl
Wlll is the output noise of the delay circuit 15 set to the delay time T (L = Wp, and the output noise W□ is delayed in phase by 2'ra = 2wp time with respect to the time To.Wl
.

はWlおよびW□、を入力信号とする減算回路の出力ノ
イズであり、パルス幅および波高値が原波形の立上がり
時間t?L=2Wpおよび波高値とほぼ等しく、発生周
期が原波形Willのそれに等しい三角波パルスに変換
される。Wlsはノイズ消去手段17の遅延回路18の
出力ノイズで、W□6が2Wpだけ遅延されることによ
り、Wl6とWlsの重なりが回避されており、両ノイ
ズパルスW1・、Wl8が掛算回路19を通ることによ
り掛算回路19の出力W1.においては周期性ノイズは
理論的には完全に消去される。゛ 第4図は第1図の実施例のノイズ除去回路のS/N比を
示す特性線図であり、第2図で説明した実験をノイズパ
ルスの立上がり、立下がシ時間を変えて繰返し行うこと
によシ得られたものであるう図において、縦軸はS/N
比を、横軸はノイズパルスの立上がプ時間τ几と移相減
算手段の遅延回路の遅延時間Taとの比A=τyL/T
dを示しており、図中曲線11Aは第1の移相減算手段
11の出力信号のS/N比を9曲線14Aは第2の移相
減算手段14の出力信号のS/N比を2曲線17Aはノ
イズ消去手段17の出力信号の37M比をに立上がる台
形波なので、S/N比中20J−Wl4(dB)で近似
される直線になる。第2の移相減算手段のS/N比曲線
14Aは被計測パルス信号のパルス列の波高値(最大値
)が2倍になるため、S/N比が曲線11Aの2倍、す
なわちS/N比中2C1ig2A(dB)で近似される
直線になる。
is the output noise of the subtraction circuit that takes Wl and W□ as input signals, and the pulse width and peak value are the same as the rise time t? of the original waveform. It is converted into a triangular wave pulse having L=2Wp, which is approximately equal to the peak value, and whose generation period is equal to that of the original waveform Will. Wls is the output noise of the delay circuit 18 of the noise canceling means 17, and by delaying W□6 by 2Wp, overlapping of Wl6 and Wls is avoided, and both noise pulses W1・, Wl8 pass through the multiplication circuit 19. By passing through the output W1. of the multiplication circuit 19. In theory, periodic noise can be completely eliminated.゛Figure 4 is a characteristic diagram showing the S/N ratio of the noise removal circuit of the embodiment shown in Figure 1, and the experiment explained in Figure 2 was repeated by changing the rise and fall times of the noise pulse. In the figure, the vertical axis is the S/N.
The horizontal axis is the ratio of the rise time τ of the noise pulse to the delay time Ta of the delay circuit of the phase shift subtraction means A=τyL/T
d, and the curve 11A in the figure shows the S/N ratio of the output signal of the first phase shift subtraction means 11; the curve 14A shows the S/N ratio of the output signal of the second phase shift subtraction means 14; Since the curve 17A is a trapezoidal wave rising at the 37M ratio of the output signal of the noise canceling means 17, it becomes a straight line approximated by 20J-Wl4 (dB) in the S/N ratio. The S/N ratio curve 14A of the second phase shift subtraction means has twice the peak value (maximum value) of the pulse train of the pulse signal to be measured, so the S/N ratio is twice that of the curve 11A, that is, the S/N It becomes a straight line approximated by 2C1ig2A (dB).

まだノイズ消去回路の出力信号のS/N比は理論的には
無限に大きい値になる筈であるが、掛算回   □路の
フィールドスルー雑音等の影響により曲線17Aで示す
よりなS/N比を示す。
Theoretically, the S/N ratio of the output signal of the noise canceling circuit should be an infinitely large value, but due to the influence of field-through noise of the multiplication circuit, the S/N ratio is higher than that shown in curve 17A. shows.

上述のように第1図のように構成されたノイズ除去回路
においては、遅延回路の遅延時間Taいいかえれば被計
測パルス信号のパルス幅に比べてノイズの立上がり、立
下がυ時間τルが遅い程良好なS/N比が得られるもの
であるが、”/’I’a =2という条件においてもノ
イズレベルを約1/10に低減でき、 /Ta=10の
条件においてはノイズレベルを1A00以下に低減する
ことができる。
As mentioned above, in the noise removal circuit configured as shown in Fig. 1, the delay time Ta of the delay circuit is in other words, the rise and fall of the noise is delayed by υ time τ compared to the pulse width of the pulse signal to be measured. Although a reasonably good S/N ratio can be obtained, the noise level can be reduced to about 1/10 even under the condition of "/'I'a = 2, and the noise level can be reduced to about 1/10 under the condition of /Ta = 10. It can be reduced to:

以上第1図の実施例に基づいてノイズ除去回路の構成な
らびに動作について説明したが、上述の動作をさらに機
能別に分類して説明する。立上がり時間τ九が遅延時間
より長いノイズに対して、第1の移相減算手段11は減
算回路13の一方の入力信号をTaだけ遅らせることに
よシノイズを低減させる機能をはたし、第2の移相減算
手段14は減算回路16の一方の入力信号をさらにT(
Lだけ遅らせることによりノイズを複数の単一パルスに
分離する機能をはたし、ノイズ消去回路17は単一パル
スの重なりを制御することによシ掛算結果を零にする機
能をはだすことにより、全体としてノイズを大幅に低減
できる機能が得られるよう構成されている。一方被計測
パルス信号に対しては、原波形の維持、いいかえれば回
路の構成部品の高周波応答性に重点が置かれるとともに
、移相減算手段たとえば2組を通ることによりたとえば
3個に増加したパルス信号を掛算回路の一方の入力信号
を遅延させることにより重なシを制御して被計測パルス
信号1個を残して他を消去する機能が有効に作用するよ
う構成されている。このように、三つの手段11,14
.17はそれぞれ独立した機能を有するので、たとえば
ノイズの立上がり時間τdとパルス信号のパルス幅Wp
の比τd/Wpが非常に大きい場合、第1の移相減算手
段だけでも充分なノイズ低減効果が得られるので、第1
の移相減算手段を独立させてノイズ消去回路を構成する
ことが可能である。
The configuration and operation of the noise removal circuit have been described above based on the embodiment shown in FIG. 1, but the above-mentioned operation will be further classified and explained by function. For noise whose rise time τ9 is longer than the delay time, the first phase shift subtraction means 11 functions to reduce the noise by delaying one input signal of the subtraction circuit 13 by Ta, and the second The phase shift subtraction means 14 further converts one input signal of the subtraction circuit 16 to T(
The noise canceling circuit 17 has the function of separating the noise into a plurality of single pulses by delaying the signal by L, and the noise canceling circuit 17 has the function of reducing the multiplication result to zero by controlling the overlap of the single pulses. , is configured to provide a function that can significantly reduce noise as a whole. On the other hand, for the pulse signal to be measured, emphasis is placed on maintaining the original waveform, in other words, on the high frequency response of the circuit components, and on the other hand, the pulse signal is increased to, for example, three by passing through two sets of phase shift subtraction means. By delaying one input signal of the signal multiplication circuit, the function of controlling overlapping signals and leaving one pulse signal to be measured and erasing the others is configured to work effectively. Thus, the three means 11, 14
.. 17 have independent functions, for example, the rise time τd of the noise and the pulse width Wp of the pulse signal.
When the ratio τd/Wp of
It is possible to construct a noise cancellation circuit by making the phase shift subtraction means independent.

第5図は第1図のノイズ除去回路の第2図とは異なる動
作を説明するための信号波形の模試図であり、遅延時間
Taのみを被計測パルスのパルス幅Wpの2倍とした例
を示したものである。図の場合、遅延回路12および1
5の遅延時間は2Wp。
FIG. 5 is a sample diagram of a signal waveform to explain the operation of the noise removal circuit in FIG. 1, which is different from that in FIG. 2, and is an example in which only the delay time Ta is twice the pulse width Wp of the pulse to be measured. This is what is shown. In the case of the figure, delay circuits 12 and 1
The delay time of 5 is 2Wp.

遅延回路18の遅延時間は4Wpに設定されておシ。The delay time of the delay circuit 18 is set to 4Wp.

その結果、W13.W15.W16.W2B等のパルス
列はそれぞれのパルス間にWpなる時間間隔を生ずるが
、ノイズ消去回路においてはP16AとP18Aが同時
刻に重なり、掛算回路19の出力側には第2図と同様に
1個の被計測パルス信号P19を出力することができる
。また’ra = 2Wpとしたことにより  r?/
Td== 4 が小さくなるので、第4図からも明らか
なように各手段11,14.17の出力信号のS/N比
は第2図のそれのほぼ1/2(6dB)程度低下する。
As a result, W13. W15. W16. A pulse train such as W2B produces a time interval of Wp between each pulse, but in the noise canceling circuit, P16A and P18A overlap at the same time, and the output side of the multiplication circuit 19 has one input as in FIG. A measurement pulse signal P19 can be output. Also, by setting 'ra = 2Wp, r? /
Since Td==4 becomes smaller, as is clear from FIG. 4, the S/N ratio of the output signal of each means 11, 14, and 17 decreases by approximately 1/2 (6 dB) of that in FIG. 2. .

このように、遅延回路12゜15の遅延時間Taは被計
測パルス信号のパルス幅Wpに必ずしも等しくする必要
はなく、被計測パルス信号のパルス幅の変動を考慮して
あらかじめ広めに設定することができる。
In this way, the delay time Ta of the delay circuit 12.degree. 15 does not necessarily need to be equal to the pulse width Wp of the pulse signal to be measured, and may be set to be wider in advance in consideration of fluctuations in the pulse width of the pulse signal to be measured. can.

また第2図、第5図においては被計測パルス信号をWp
=5Qnaの台形波とした場合の例について説明したが
、被計測パルス信号波形が第7図のような減衰波形であ
っても、また波形に振動分を含むものであっても、出力
回路には原波形に近い被計測パルス信号を出力すること
ができる。ただし、振動分を含む被計測パルス信号を原
波形に近い形で出力するためには、回路の構成部品に高
周波応答性のすぐれたものを用いなければならないこと
はいうまでもないことである。
In addition, in FIGS. 2 and 5, the pulse signal to be measured is Wp
Although we have explained an example in which a trapezoidal waveform with =5Qna is used, even if the pulse signal waveform to be measured is an attenuated waveform as shown in Fig. 7, or even if the waveform contains a vibration component, the output circuit can output a measured pulse signal close to the original waveform. However, it goes without saying that in order to output a pulse signal to be measured containing vibration components in a form close to the original waveform, circuit components with excellent high frequency response must be used.

〔発明の効果〕〔Effect of the invention〕

本発明は前述のように、被計測パルス信号の持続時間に
見合う遅延時間にあらかじめ設定された遅延回路と減算
回路とからなり前記遅延時間よシ長い立上がり、立下が
シ時間のノイズに対して減衰機能を有する第1の移相減
算手段と、この減算手段と同様に構成され第1の移相減
算手段の出力ノイズをパルス幅が短縮された複数の単一
パルス゛に分離する機能を有する第2の移相減算手段と
、前記第1.第2の移相減算手段の総遅延時間に等しい
遅延時間に設定された遅延回路と掛算回路とからなり前
記単一パルスに分離されたノイズパルスを消去する機能
を有するノイズ消去手段とでノイズ除去回路を構成した
。その結果、被計測パルス信号の持続時間よ、り長い立
上がり、立下がシ時間を有する単発性9周期性ノイズを
低減あるいは除去できるとともに、第11第2の移相減
算手段を通ることによシ複数個のパルス列に増えた被計
測パルス信号はノイズ消去手段を通ることによシ一つの
原波形に相似な被計測パルス信号に逆変換され、出力回
路を介してS/N比が改善された原波形に近い被計測パ
ルス信号を出力できるノイズ除去回路を提供することが
できる。また本発明のノイズ除去回路は、フィルタを用
いた従来の回路に比べて被計測パルス信号を変歪させる
ことなくノイズの低減効果が得られるとともに、遅延線
と加算回路からなる従来のノイズ除去回路では充分でな
かったパルス信号よシ長い立上シ時間を有する種々の時
間幅の単発性および周期性ノイズそれぞれに対して同時
に低減効果を持ち、かつ遅延回路の遅延時間をあらかじ
め設定できる利便性が得1   られる。
As described above, the present invention comprises a delay circuit and a subtraction circuit, which are preset to a delay time commensurate with the duration of the pulse signal to be measured. a first phase shift subtraction means having an attenuation function; and a second phase shift subtraction means configured similarly to the subtraction means and having a function of separating the output noise of the first phase shift subtraction means into a plurality of single pulses having shortened pulse widths. 2 phase shift subtraction means; Noise removal means includes a delay circuit set to a delay time equal to the total delay time of the second phase shift subtraction means and a multiplication circuit, and has a function of erasing the noise pulse separated into the single pulse. The circuit was constructed. As a result, it is possible to reduce or eliminate single-shot periodic noise whose rise and fall times are longer than the duration of the pulse signal to be measured, and also because it passes through the eleventh second phase shift subtraction means. The pulse signal to be measured, which has increased to a plurality of pulse trains, is inversely converted into a pulse signal to be measured similar to one original waveform by passing through a noise canceling means, and the S/N ratio is improved through the output circuit. Accordingly, it is possible to provide a noise removal circuit that can output a measured pulse signal close to the original waveform. In addition, the noise removal circuit of the present invention can achieve a noise reduction effect without distorting the pulse signal to be measured compared to a conventional circuit using a filter. It has the effect of simultaneously reducing single-shot and periodic noise of various time widths that have a longer rise time than pulse signals, which was not sufficient with pulse signals, and it also has the convenience of being able to set the delay time of the delay circuit in advance. Gain 1 You can get it.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示すノイズ除去回路のブロッ
ク図、第2図は第1図のノイズ除去回路の動作を説明す
るための信号波形図で入力信号が単発性ノイズを含む場
合の例、第3図は第1図のノイズ除去回路の周期性ノイ
ズに対する動作を説明するための信号波形図、第4図は
第1図のノイズ除去回路のS/N比を示す特性線図、第
5図は第2図とは遅延時間の設定条件が異なる場合の信
号波形図、第6図は従来の改良されたノイズ除去回路の
構成図で電カケープルの部分放電試験回路への適用例、
第7図は第6図のノイズ除去回路の動作を説明するため
の信号波形図である。 10・・・入力回路、11・・・第1の移相減算手段、
14・・・第2の移相減算手段、12.15・・・遅延
回路、13.16・・・減算回路、17・・・ノイズ消
去手段、18・・・ノイズ消去手段の遅延回路、19・
・・掛算回路、20・・・出力回路、Wlo、N12・
・・N20・・・各部出力信号、Plo + ”11”
・・P、・・・・被計測パルス信号、N10.N12・
・・N20・・・ノイズパルス、Wp・・・被計測パル
ス信号の持続時間(パルス幅)、τ九第3図 第4図 第5図
Fig. 1 is a block diagram of a noise removal circuit showing an embodiment of the present invention, and Fig. 2 is a signal waveform diagram for explaining the operation of the noise removal circuit shown in Fig. 1 when the input signal contains single-shot noise. For example, FIG. 3 is a signal waveform diagram for explaining the operation of the noise removal circuit in FIG. 1 against periodic noise, and FIG. 4 is a characteristic diagram showing the S/N ratio of the noise removal circuit in FIG. 1. Fig. 5 is a signal waveform diagram when the delay time setting conditions are different from Fig. 2, and Fig. 6 is a configuration diagram of a conventional improved noise removal circuit, which is an example of application to a partial discharge test circuit of a power cable.
FIG. 7 is a signal waveform diagram for explaining the operation of the noise removal circuit of FIG. 6. 10... Input circuit, 11... First phase shift subtraction means,
14... Second phase shift subtraction means, 12.15... Delay circuit, 13.16... Subtraction circuit, 17... Noise erasing means, 18... Delay circuit of noise erasing means, 19・
・Multiplication circuit, 20 ・Output circuit, Wlo, N12・
・・N20・・・Each part output signal, Plo + “11”
... P, ... Pulse signal to be measured, N10. N12・
...N20...Noise pulse, Wp...Duration (pulse width) of pulse signal to be measured, τ9 Fig. 3 Fig. 4 Fig. 5

Claims (1)

【特許請求の範囲】 1)持続時間があらかじめ定まる時間範囲にある単発性
の被計測パルス信号に単発性あるいは周期性の電気的ノ
イズが重畳した入力信号を受け、立上り、立下り時間が
前記時間範囲を超える前記ノイズを低減、除去するとと
もにほぼ原波形に近い前記被計測パルス信号を出力する
ものであって、遅延時間が前記時間範囲内の所定時間に
あらかじめ設定された遅延回路ならびにこの遅延回路の
入力信号および出力信号を入力信号とする減算回路を複
数組互いに縦続接続してなる移相減算手段と、この移相
減算手段の出力側に設けられ移相減算手段の総遅延時間
に相応する遅延時間を有する遅延回路ならびにこの遅延
回路の入力信号および出力信号を入力信号とする掛算回
路からなるノイズ消去手段と、このノイズ消去手段の出
力側に設けられた出力回路とを備えたことを特徴とする
ノイズ除去回路。 2)特許請求の範囲第1項記載のものにおいて、出力回
路が開平回路からなることを特徴とするノイズ除去回路
[Scope of Claims] 1) An input signal in which a single-shot or periodic electrical noise is superimposed on a single-shot pulse signal to be measured whose duration is within a predetermined time range is received, and the rise and fall times are set within the above-determined time range. A delay circuit that reduces and removes the noise exceeding the range and outputs the measured pulse signal that is close to the original waveform, the delay circuit having a delay time set in advance to a predetermined time within the time range, and this delay circuit. phase shift subtraction means formed by cascade-connecting a plurality of sets of subtraction circuits whose input signals are the input signal and output signal of It is characterized by comprising a noise canceling means consisting of a delay circuit having a delay time and a multiplication circuit whose input signals are input signals and output signals of the delay circuit, and an output circuit provided on the output side of the noise canceling means. noise removal circuit. 2) The noise removal circuit according to claim 1, wherein the output circuit is comprised of a square root circuit.
JP59203686A 1984-09-28 1984-09-28 Noise eliminating circuit Granted JPS6181021A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP59203686A JPS6181021A (en) 1984-09-28 1984-09-28 Noise eliminating circuit
US06/780,170 US4710705A (en) 1984-09-28 1985-09-26 Noise removal circuit for use in a partial discharge measuring device of a high voltage apparatus
DE8585306863T DE3569988D1 (en) 1984-09-28 1985-09-26 Partial discharge measuring device
EP85306863A EP0180322B1 (en) 1984-09-28 1985-09-26 Partial discharge measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59203686A JPS6181021A (en) 1984-09-28 1984-09-28 Noise eliminating circuit

Publications (2)

Publication Number Publication Date
JPS6181021A true JPS6181021A (en) 1986-04-24
JPH0441845B2 JPH0441845B2 (en) 1992-07-09

Family

ID=16478161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59203686A Granted JPS6181021A (en) 1984-09-28 1984-09-28 Noise eliminating circuit

Country Status (1)

Country Link
JP (1) JPS6181021A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113227801A (en) * 2018-11-07 2021-08-06 威电科技有限公司 Derivative voltage and current sensing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113227801A (en) * 2018-11-07 2021-08-06 威电科技有限公司 Derivative voltage and current sensing device

Also Published As

Publication number Publication date
JPH0441845B2 (en) 1992-07-09

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