JPS60380A - Detecting circuit of moving object - Google Patents
Detecting circuit of moving objectInfo
- Publication number
- JPS60380A JPS60380A JP10958783A JP10958783A JPS60380A JP S60380 A JPS60380 A JP S60380A JP 10958783 A JP10958783 A JP 10958783A JP 10958783 A JP10958783 A JP 10958783A JP S60380 A JPS60380 A JP S60380A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- adder
- signal
- coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
- G01S13/50—Systems of measurement based on relative movement of target
- G01S13/52—Discriminating between fixed and moving objects or between objects moving at different speeds
- G01S13/522—Discriminating between fixed and moving objects or between objects moving at different speeds using transmissions of interrupted pulse modulated waves
- G01S13/524—Discriminating between fixed and moving objects or between objects moving at different speeds using transmissions of interrupted pulse modulated waves based upon the phase or frequency shift resulting from movement of objects, with reference to the transmitted signals, e.g. coherent MTi
- G01S13/526—Discriminating between fixed and moving objects or between objects moving at different speeds using transmissions of interrupted pulse modulated waves based upon the phase or frequency shift resulting from movement of objects, with reference to the transmitted signals, e.g. coherent MTi performing filtering on the whole spectrum without loss of range information, e.g. using delay line cancellers or comb filters
Landscapes
- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、有限ヒツト数の受信信号を用いて固定目標の
消去を行い、移動目標を検出するレーダ装置の移動目標
検出回路（Ｍｏｖｉｎｇ Ｔａｒｇｅｔ Ｉｎｄｉｃａ
−ｔｏｒ ； 以下ＭＴ１回路と称す）に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a moving target detection circuit (Moving Target Indica
-tor; hereinafter referred to as MT1 circuit).
従来この種の装置として、第１図に示すものがあった。A conventional device of this type is shown in FIG.
図は、Ｎ＋１ヒツトの受信信号を用いてを８段縦続接続
したＮ重のフィルタと、スイッチ（２９及び除算器ので
構成される。なお、図中太線で示す矢印は複素信号を表
わす。The figure is composed of N-fold filters cascaded in eight stages using N+1 received signals, a switch (29), and a divider. Note that the thick arrows in the figure represent complex signals.
次に動作について説明する。レーダの受信機（図示せず
）で受信され、位相検波された受信ビデオの複素信号Ｅ
ｉ（ｔ）は、遅延回路Ｃｌ１ｌで１送信周期遅延され、
符号を反転された後、加算器（功で次の送信周期（次の
ヒツト）の受信信号と加算される。Next, the operation will be explained. The complex signal E of the received video received at the radar receiver (not shown) and phase detected.
i(t) is delayed by one transmission period in the delay circuit Cl1l,
After its sign is inverted, it is added to the received signal of the next transmission period (next hit) using an adder.
この回路をＮ段通った後、除算器＠て入出力の振１回路
では、Ｎ＋１ヒツトの入力が終るまでは固定目標が消去
されないため、Ｎ＋１ヒツトの入力が終った時点でスイ
ッチ（２１）がゲート・パルス（Ｇ、Ｐ）により接にさ
れ、信号が出力される。After passing through this circuit in N stages, the input and output of the divider @1 circuit does not erase the fixed target until the input of N+1 hits is completed, so the switch (21) is turned on when the input of N+1 hits is completed. It is connected by gate pulses (G, P) and a signal is output.
移動目標からの受信信号は、目標の移動によるドツプラ
偏移を受けており、位相検波さ４ｔた信号Ｅｉ（りは、
振幅Ａと〜う周波数ωにより次式で表わされる。The received signal from the moving target is subjected to Doppler shift due to the movement of the target, and the signal Ei after phase detection is 4t.
It is expressed by the following equation using the amplitude A and the frequency ω.
Ｅｉ（す＝Ａ−ｅＪ” ・・・・・・・・・・・・・・
・・−・・・・・・・（１）また、遅延回路（１１）は
ｚ−１で表わされるため、１重フィルタ叫の伝達関数Ｈ
１（Ｚ）は
Ｈｌ （Ｚ） ＝ １− Ｚ ’ −＝−１−−−−−
−−−（２）となり、この（２）式で表わされる１重フ
イルりＱＯ）をＮ段縦続接続したときの伝達関数ＨＮ（
Ｚ） ＋よＨＮ（Ｚ） ＝ （１−Ｚ ”）Ｎ、・・・
・・・・・・・・・・・・・・・・・・・・（３）とな
る。Ei (S=A-eJ” ・・・・・・・・・・・・・・・
...... (1) Also, since the delay circuit (11) is represented by z-1, the transfer function H of the single filter signal is
1(Z) is Hl (Z) = 1- Z' -=-1-----
---(2) is obtained, and the transfer function HN(
Z) +yoHN(Z) = (1-Z ”)N,...
・・・・・・・・・・・・・・・・・・・・・(3)
また、遅延回路Ｑｌｌは、送信周期Ｔの遅延を行うため
、
ｚ ＝ｅ３ｃａＴ ・・・・・・・・・・・・・・・・
・・・・・・・・（４）で表わされ、第１図に示すＭＴ
１回庁各の出力Ｅｏ（ｔ）は、８重フィルタの出力を除
算器ので一に除算Ｎ
した値であるから、
臥′）′７°Ｅｉ （ｔ ）”ＨＮ（Ｚ）となる。In addition, since the delay circuit Qll delays the transmission period T, z = e3caT . . .
......(4) and the MT shown in Figure 1
Since the output Eo(t) of each filter is the value obtained by dividing the output of the octet filter by 1 by the divider N, it becomes 臥')'7°Ei(t)''HN(Z).
このとき、出力の振幅ＩＥ０１は
１Ｅｏｌ ＝＝ Ａ−ｌｓｉｎ匹ＩＮ・・・・・・・・
・・・・・・・・・・・・・・・・（６）となり、固定
目標（ω＝０）は消去され、移動目標（ドツプラ周波数
ω）は出力される。At this time, the output amplitude IE01 is 1Eol == A-lsin IN...
(6) The fixed target (ω=0) is deleted and the moving target (Doppler frequency ω) is output.
また、（６）式のωＴに対する出力振幅ＩＥ０１を第２
図に示す。ＭＴＩ回路の周波数特性は、フィルタの段数
によって変化し、段数Ｎが大きくなるほど（多重フィル
タにするほど）固定目標の消去性能は良くなる。In addition, the output amplitude IE01 for ωT in equation (6) is
As shown in the figure. The frequency characteristics of the MTI circuit change depending on the number of stages of the filter, and the larger the number of stages N (the more multiple filters are used), the better the fixed target erasing performance becomes.
従来のＭＴＩ回路は以上のように構成されているので、
固定目標の消去性能を良くするため多重ＭＴＩ回路を構
成するには、同一構成の回路（１重フィルタ）を多数縦
続接続する必要があった。Since the conventional MTI circuit is configured as described above,
In order to configure a multiple MTI circuit to improve the fixed target erasing performance, it is necessary to cascade a large number of circuits (single filters) with the same configuration.
この発明は、上記のような従来のものの欠点を除去する
ためになされたもので、従来の１重フィルタと同等の規
模の遅延回路と加算器により構成される１組のフィルタ
の前に乗算器を設け、乗算係数をヒツト毎に制御して該
係数と受信信号とを乗算し、これを上記フィルタに入力
するようにすることにより、任意のヒツト数Ｎ＋１に対
するＮ重のフィルタが１組のフィルタで構成可能となり
、小型で安価な、しかも上記乗算係数を切り換えること
により、任意の段数相当のＭＴＩ回路に切り換えること
のできるＭＴ１回路を提供することを目的としている。This invention was made in order to eliminate the drawbacks of the conventional filters as described above, and includes a multiplier in front of a set of filters consisting of a delay circuit and an adder of the same scale as the conventional single filter. By controlling the multiplication coefficient for each hit, multiplying the coefficient by the received signal, and inputting this to the above filter, N-fold filters for any number of hits N+1 can be combined into one set of filters. It is an object of the present invention to provide an MT1 circuit which is small and inexpensive, and which can be switched to an MTI circuit corresponding to an arbitrary number of stages by switching the multiplication coefficient.
以下、この発明の一実施例を図について説明する。An embodiment of the present invention will be described below with reference to the drawings.
第３図において、（１）は乗算器、（２）は乗算器（１
）の乗算係数及び除算器■の除算係数を発生する係数発
生回路、（１１）は信号を１送信周期だけ遅延させる遅
延回路、Ｏ２は乗算器（１）からの信号と遅延回路αυ
からの信号を加算する加算器であり、上記遅延回路ＯＢ
及び加算器（１２）により１組のフィルタ（１０１が構
成されている。（２１）はフィルタ処理の終った時点で
信号を出力するためのスイッチ、＠は入出力の信号振幅
を揃えるための除算器である。なお、図中太線で示す矢
印は複素信号を表わす。In Figure 3, (1) is a multiplier, (2) is a multiplier (1
), a coefficient generation circuit that generates the multiplication coefficient of the divider ■, and a coefficient generation circuit that generates the division coefficient of the divider ■, (11) is a delay circuit that delays the signal by one transmission period, and O2 is the signal from the multiplier (1) and the delay circuit αυ.
This is an adder that adds signals from the delay circuit OB.
and an adder (12) constitute a set of filters (101). (21) is a switch for outputting a signal at the end of filter processing, and @ is a divider for equalizing input and output signal amplitudes. Note that the bold arrows in the figure represent complex signals.
次に動作について説明する。初期状態では、遅延回路（
１１＋の内容は１０＃にしておく。受信ビデオの複素信
号Ｅｉ（りは、乗算器（１）で、係数発生回路（２）に
よりＭ１１回路の段数Ｎに従って、ヒツト毎に発生され
る係数とヒツト毎に乗算される。加算器０ｚては乗算器
（１）から送られる信号と遅延回路（１１）から送られ
る信号との加算を行い、この信号は遅延回路圓で再び送
信周期の遅延を受ける。Ｎ＋１ヒツト分の上記の処理が
終った時点で、ゲート・パルス（Ｇ−Ｐ）によりスイッ
チ＋２１）は接にされ、該処理の終った信号は、係数発
生回路（２）でフィルタ段数Ｎに従って、入出力の信号
の振幅を揃えるために発生される除算係数により、除算
器ので除算されで出力される。Next, the operation will be explained. In the initial state, the delay circuit (
The content of 11+ is set to 10#. The complex signal Ei of the received video is multiplied for each hit by a coefficient generated for each hit by the coefficient generation circuit (2) according to the number of stages N of the M11 circuit in the multiplier (1).Adder 0z performs addition of the signal sent from the multiplier (1) and the signal sent from the delay circuit (11), and this signal is again delayed by the transmission cycle in the delay circuit circle.The above processing for N+1 hits is completed. At that point, the switch +21) is connected by the gate pulse (G-P), and the processed signal is sent to the coefficient generation circuit (2) in order to equalize the amplitude of the input and output signals according to the number of filter stages N. is divided by the division coefficient generated by the divider and output as .
ここで、係数発生回路（２）で発生される乗算係数をｋ
ｎ（ｎ：ヒツト番号、１．２，３．−・°−Ｎ＋１ ）
とすると、該乗算係数ｋｎは
（１−Ｘ）Ｎ−ｋＮ＋１十ｋＮＸ十ｋＮ−ＩＸ２＋ ・
・・・・・・・・・・ｋ２ｘゞ−１十ｋｌＸＮ ・・・
・・・・・・・・・（７）で表わされる値とする。例と
して、
Ｎ重１（１重ＭＴＩ ） ： ｋ、＝−１、ｋ、＝１Ｎ
、２（２重ＭＴＩ）：にに１＋ ｋｔ＝ ２ 、 ｋ、
＝ ＩＮ＝３ （３重ＭＴＩ ） ： ｋ、＝−ｊ 、
ｋ、＝＝３ 、 ｋ３＝−３。Here, the multiplication coefficient generated by the coefficient generation circuit (2) is k
n (n: human number, 1.2, 3.-・°-N+1)
Then, the multiplication coefficient kn is (1-X)N-kN+10kNX10kN-IX2+
・・・・・・・・・k2xゞ-10klXN ・・・
......The value is expressed by (7). As an example, N-fold 1 (single-fold MTI): k, = -1, k, = 1N
, 2 (double MTI): 1 + kt= 2 , k,
= IN=3 (triple MTI): k, =-j,
k,==3, k3=-3.
ｋ４＝１
Ｎ−＝４（４重ＭＴＩ ） ： ｋ、＝ｌ 、 ｋ、＝
−４、ｋ３−＝５ 。k4=1 N-=4 (quadruple MTI): k,=l, k,=
-4, k3-=5.
ｋ４＝−４、ｋ、＝＝ １ である。k4=-4,k,==1 It is.
ある。be.
このとき、本実施例によるＭＴＩ回路の出力勤（【）は
十ｋＮＺ ’ 十ｋＮ−１−８）
となり、（５）式で表わされる従来方式のＭＴ１回路と
同じ出力が得られることとなる。At this time, the output force ([) of the MTI circuit according to this embodiment is 10 kNZ' 10 kN-1-8), and the same output as the conventional MT1 circuit expressed by equation (5) can be obtained.
このような本実施例装置では、係数発生回路でヒツト毎
に乗算器の乗算係数を制御し、任意のヒツト数Ｎ＋１に
対するＮ重の消去フィルタを１組のフィルタで構成可能
としたので、多重フィルタの機能を有するＭＴ１回路を
非常に小型で安価にすることができる。またそのフィル
タの段数を任意に制御できるので、例えはフェーズドア
レイレーダ装置において、上方からのクラッタ等の少な
い反射波に対しては段数を少なく、枦方向／Ｊ）らのク
ラッタ等を多く含む反射波に対しては段数を多くして、
１つのＭＴＩ回路でそのフィルタ性能を適宜に変化させ
ることができる。In the device of this embodiment, the coefficient generation circuit controls the multiplication coefficient of the multiplier for each hit, and N-fold cancellation filters for any number of hits N+1 can be configured with one set of filters. The MT1 circuit having this function can be made very small and inexpensive. In addition, since the number of stages of the filter can be controlled arbitrarily, for example, in a phased array radar device, the number of stages is reduced for reflected waves with little clutter etc. from above, and the number of stages is reduced for reflected waves with a lot of clutter etc. from the direction /J). For waves, increase the number of stages,
One MTI circuit can change its filter performance as appropriate.
なお、上記実施例では、入出力の振幅を揃えるため、除
算器■を有する例を示したが、係数発生回路（２）で発
生する乗算係数を、ｋ ｎ、ｆ４ とすることにより、
除算器輯）を省くことができる。このとき、回路がディ
ジタルで構成されている場合は切り捨てによる誤差が生
じるが、ビットの成長によるオーバーフローが生じない
ため、回路の演算ビット数を少なくできる利点もあり、
小型化の効果が太きい。Note that in the above embodiment, an example is shown in which the divider ■ is provided in order to equalize the input and output amplitudes, but by setting the multiplication coefficients generated in the coefficient generation circuit (2) to k n, f4,
(divider) can be omitted. At this time, if the circuit is constructed digitally, an error will occur due to truncation, but since no overflow will occur due to bit growth, there is also the advantage that the number of operation bits in the circuit can be reduced.
The effect of miniaturization is significant.
以上のように、この発明によれば、従来、１重フィルタ
を多段に縦続接続して構成されていた多重フィルタを、
乗算器、係数発生回路及び従来の１重フィルタに相当す
る規模の１組のフィルタにより構成可能としたので、回
路が小型、安価にてきる効果がある。また、係数発生回
路で発生する係数を変化させることにより、任意の段数
相当のＭＴ１回路が１組のフィルタで構成できる効果が
ある。As described above, according to the present invention, a multiplex filter, which was conventionally configured by cascading single filters in multiple stages, can be replaced with
Since it can be constructed from a multiplier, a coefficient generating circuit, and a set of filters of a size equivalent to a conventional single filter, the circuit can be made smaller and less expensive. Furthermore, by changing the coefficients generated by the coefficient generation circuit, there is an effect that an MT1 circuit corresponding to an arbitrary number of stages can be configured with one set of filters.
第１図は、従来のＭＴ１回路の構成図、第２図は、ＭＴ
Ｉ回路の周波数特性を示す図、第３図は、本発明の一実
施例によるＭＴＩ回路の構成図である。
（１）・・・乗算器、（２）・・・係数発生回路、Ｏト
・・フィルタ、０ト・・遅延回路、Ｏ２・・・加算器
なお、図中、同一符号は同一、又は相当部分を示す。
代理人 大 岩 増 雄
５６Figure 1 is a configuration diagram of a conventional MT1 circuit, and Figure 2 is a diagram of a conventional MT1 circuit.
FIG. 3, a diagram showing the frequency characteristics of the I circuit, is a configuration diagram of an MTI circuit according to an embodiment of the present invention. (1)... Multiplier, (2)... Coefficient generation circuit, Oto... Filter, Oto... Delay circuit, O2... Adder. Note that the same symbols in the figures are the same or equivalent. Show parts. Agent Masuo Oiwa56
Claims (1)
を行い移動目標を検出するレーダ装置の移動目標検出回
路において、１重フィルタを８段縦続接続した８重フィ
ルタの伝達関数の各係数をヒツト毎に発生する係数発生
回路と、各ヒツト毎の受信信号と上記係数発生回路の出
力とを乗算する乗算器と、該乗算器の出力を一万の入力
とする加算器及びこの加算器の出力を１送信周期だけ遅
延させその出力を上記加算器の他の入力とする遅延回路
からなり固定目標からの受信信号を消去するための１組
のフィルタとを備え、任意のヒツト数Ｎ＋１に対するＮ
重の固定目標消去フィルタが構成可能であることを特徴
とする移動目標検出回路。(1) In a moving target detection circuit of a radar device that uses a finite number of received signals to eliminate fixed targets and detect moving targets, each coefficient of the transfer function of an octuplet filter in which 8 stages of single filters are connected in cascade. a coefficient generating circuit that generates for each hit, a multiplier that multiplies the received signal for each hit by the output of the coefficient generating circuit, an adder that uses the output of the multiplier as an input of 10,000, and this adder. The output of the adder is made up of a delay circuit that delays the output of the adder by one transmission period and uses the output as the other input of the adder, and a set of filters for canceling the received signal from the fixed target. N
A moving target detection circuit characterized in that a heavy fixed target elimination filter is configurable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10958783A JPS60380A (en) | 1983-06-16 | 1983-06-16 | Detecting circuit of moving object |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10958783A JPS60380A (en) | 1983-06-16 | 1983-06-16 | Detecting circuit of moving object |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60380A true JPS60380A (en) | 1985-01-05 |
Family
ID=14514040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10958783A Pending JPS60380A (en) | 1983-06-16 | 1983-06-16 | Detecting circuit of moving object |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60380A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3000214A1 (en) * | 1979-12-21 | 1981-07-09 | Pilot Ink Co., Ltd., Nagoya, Aichi | Ballpoint pen tip |
| US4672754A (en) * | 1983-08-18 | 1987-06-16 | Patoflex Corporation | Shoe sole |
| US4882495A (en) * | 1985-01-12 | 1989-11-21 | Hitachi Medical Corporation | Scintillation camera |
-
1983
- 1983-06-16 JP JP10958783A patent/JPS60380A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3000214A1 (en) * | 1979-12-21 | 1981-07-09 | Pilot Ink Co., Ltd., Nagoya, Aichi | Ballpoint pen tip |
| DE3000214C3 (en) * | 1979-12-21 | 1991-06-13 | Pilot Ink Co Ltd | PEN |
| US4672754A (en) * | 1983-08-18 | 1987-06-16 | Patoflex Corporation | Shoe sole |
| US4882495A (en) * | 1985-01-12 | 1989-11-21 | Hitachi Medical Corporation | Scintillation camera |
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