RU117793U1 - DIAGRAM-FORMING DEVICE FOR MULTI-BEAM RECEPTION OF ULTRASONIC SIGNALS - Google Patents

Abstract

1. A diagram-forming device for multi-beam reception of ultrasonic signals, containing a receiving-transmitting module, which includes receiving channels of signals from elements of an ultrasonic sensor, each receiving channel of signals is electrically connected through an individual analog-to-digital converter with a primary random access memory of the FIFO type, which in turn is connected to the primary filter-interpolator, and also containing the secondary random access memory of the FIFO type, multipliers, multiplexers and adders, characterized in that the primary random access memory of the FIFO type is connected to the primary block of shift registers, the outputs of the primary filter-interpolator and the primary block of shift registers are connected to the corresponding inputs of two secondary filter-interpolators, while the primary block of shift registers, the primary filter-interpolator and secondary filter-interpolators are connected through the secondary blocks of shift registers with the corresponding inputs of the shapers beams, each of which is connected to a corresponding channel adder and includes a series-connected multiplexer, a secondary random access memory of the FIFO type and a multiplier; in addition, each interpolator filter is a filter interpolator with a fixed symmetric impulse response. ! 2. The diagram-forming device according to claim 1, characterized in that the electrical connection between the elements of the device is made by means of data buses. ! 3. The diagram-forming device according to claim 1, characterized in that the number of receiving signal channels corresponds to the number of simultaneously used

Description

This technical solution relates to the field of medical instrumentation, in particular, to devices for ultrasonic echolocation of internal organs, and can be used in medical diagnostic systems.

It is known in the art that a multi-path ultrasound beamforming device (DFU) is provided to provide a high frame rate for the image being generated, each channel of which includes an analog-to-digital converter (ADC), a signal delay generation module, an apodization module, and adders (United States Patent 5,905,692 publ. 05/18/1999). The disadvantage of this technical solution is that when implementing multipath reception, an increase in the number of receiving channels is associated with a proportional increase in the number of filter interpolators and, accordingly, hardware costs, as well as the cost of the device.

Also known from the prior art is a diagram-forming device for multipath reception of ultrasonic signals, comprising a receiving and transmitting module, which includes receiving channels of signals from sensor elements, each receiving channel of signals is electrically connected through an individual analog-to-digital converter with primary random access memory of the FIFO type , which, in turn, is connected to the filter-interpolator, as well as containing secondary random access memory of the FIFO type, multipliers, multiplexers and adders (see, on p., United States Patent 6,695,783, publ. 24.02.2004).

In this technical solution, an increase in the number of receiving channels does not lead to a proportional increase in the number of filter interpolators. However, the disadvantage of this device is the excessive hardware costs for generating interpolated signal samples, since the implemented generation of interpolated signal samples does not take into account the fact that when implementing a fractional signal delay equal to 0.5 of the sampling interval, the number of multipliers due to the use of the symmetrical impulse response of the filter-interpolator can be halved, as well as the fact that there is no need to perform computational operations when the fractional delay s Nala is zero. The disadvantage is also the excessive hardware costs associated with the need for constant adjustment of the coefficients of the filter-interpolator with the cycle of arrival of the signal samples.

The task to which the claimed technical solution is directed is to reduce hardware costs to improve the dynamics of the formation of ultrasound images.

This problem is solved due to the fact that in the claimed diagram-forming device for multipath reception of ultrasonic signals, containing a receiving-transmitting module, which includes receiving signal channels from the sensor elements, each signal receiving channel is electrically connected through an individual analog-to-digital converter with primary memory of the FIFO type, which in turn is connected to the primary filter-interpolator, and also containing secondary random access memory of the FIFO type, multipliers, multiplier tiplexers and adders, according to the utility model, the primary RAM of the FIFO type is connected to the primary block of shift registers, the outputs of the primary filter interpolator and the primary block of shift registers are connected to the corresponding inputs of two secondary filter interpolators, while the primary block of shift registers, the primary filter the interpolator and secondary filters-interpolators are connected through the secondary blocks of the shift registers with the corresponding inputs of the beam shapers, each of which is connected to tvetstvuyuschim adder channels and includes serially connected multiplexor, the secondary FIFO type memory and a multiplier, in addition, each filter interpolator is an interpolator filter with a symmetric impulse response fixed.

The electrical connection between the elements of the device can be made via data buses.

The number of receiving channels of the signals may correspond to the number of simultaneously used elements of the ultrasonic sensor.

The technical result provided by the given set of features is to reduce hardware costs to improve the dynamics of the formation of ultrasound images due to the structural design of the device, namely due to the fact that the primary random access memory type FIFO is connected to the primary filter-interpolator and to the primary block of shift registers, outputs the primary filter-interpolator and the primary block of shift registers are connected to the corresponding inputs of two secondary filter-interpolators, p In this case, the primary block of shift registers, the primary filter interpolator and the secondary filter interpolators are connected through the secondary blocks of the shift registers with the corresponding inputs of the beam former, each of which is connected to the corresponding adder of channels and includes a series-connected multiplexer, a secondary random access memory of the FIFO type and a multiplier, and also due to the fact that each filter interpolator is a filter interpolator with a fixed symmetrical impulse response.

The design features of the device listed above make it possible to reduce hardware costs to increase the frame rate of the generated ultrasound image, since the computational resources of filter interpolators are fully loaded by organizing the computing process so that at any time the filter interpolator is used only to form a fractional delay and not idle when it is not necessary to form a fractional delay of the signal. In addition, the use of filter interpolators with a fixed symmetrical impulse response allows you to halve the number of multipliers, and also, since unlike the analog in the calculation process, filter interpolators do not change their impulse response, it is possible to use a simplified structure of multipliers that implement the operation multiplications in the structure of the filter-interpolator only by a fixed coefficient.

The essence of the claimed device is illustrated by drawings that do not cover and, moreover, do not limit the scope of claims for this decision, but are only illustrative materials of a particular case of the device. The drawings show:

Figure 1 - block diagram of the device;

Figure 2 is a timing diagram of the formation of the results of a smooth signal delay;

Figure 3 is a timing diagram of the operation of the device in the mode of additional beam forming by time multiplexing.

The device includes a receiving-transmitting module, which includes N receiving channels of signals 1/1 ... 1 / N in accordance with the number of simultaneously used sensor elements.

Each receiving channel of signals 1 / j, j = 1,2, ..., N is electrically connected through an individual analog-to-digital converter 2 with primary RAM 3 of the FIFO type. Primary random access memory 3 of the FIFO type is connected to the primary block of shift registers 4 and to the primary filter interpolator 5. The outputs of the primary filter interpolator 5 and to the primary block of shift registers 4 are connected to the corresponding inputs of two secondary filter interpolators 6, 7. The primary block of shift registers 4, the primary filter interpolator 5 and the secondary filter interpolators 6, 7 are connected through the corresponding secondary blocks of the shift registers 8, 9, 10, 11 with the corresponding inputs of the beam shapers 12. Each beamformer 12 includes a series-connected multiplexer 13, a secondary RAM 14 of the FIFO type and a multiplier 15 and is connected to a corresponding adder 16 channels. The number L of beam shapers 12 is equal to the number L of adders 16 channels, that is, for L beam shapers 12/1 ... 12 / L, L channel adders 16/1 ... 16 / L are used. Each filter interpolator 5, 6, 7 is a filter interpolator with a fixed symmetrical impulse response.

The device provides multipath reception of an ultrasonic signal based on the dynamic tuning of the signal delay system represented by a sequence of digital data. Moreover, coarse tuning of the signal delay up to the sampling step of the input signal is carried out using primary and secondary random access memory 3, 14 of the FIFO type, and a smooth (fractional) delay with higher accuracy than the signal sampling step is performed using the primary and secondary filter interpolators 5, 6, 7. The primary and secondary filter interpolators 5, 6, 7 form all possible smooth signal delays, which are then used to form all receiving beams. The transmitting and receiving module is made mainly in the form of a housing.

According to the results of many studies (United States Patent 6,695,783, published February 24, 2004), it is believed that the minimum step of changing the signal delay, a further decrease of which will not lead to a noticeable increase in the quality of the image formed, is l / (16f _c ), where f _c - operating frequency of the sensor. In this case, the interpolation coefficient K is given by the relation:

where f _S is the sampling frequency of the ultrasonic signal.

If the operating frequency of the sensor f _C does not exceed 12.5 MHz, which corresponds to the overwhelming number of practical applications, then, as follows from formula (1), with the sampling frequency of the ultrasonic signal f _S = 50 MHz, it is enough that the interpolation coefficient K is 4. In this case, the filter interpolator should provide a signal delay in increments of 0.25T _S , where T _S = 1 / f _S is the sampling rate of the ultrasonic signal, i.e. form a set of fractional signal delays: 0.25T _S , 0.5T _S , 0.75T _S. The interpolation coefficient K, equal to 4, can also be used for ultrasonic sensors with a higher operating frequency by increasing the speed of the ADC. For example, if you use ultrasonic sensors with a maximum operating frequency of 15 MHz, then for K = 4 it is enough for the ADC to provide a signal sampling frequency f _S = 60 MHz.

The device operates as follows. In accordance with the block diagram of FIG. 1, in each receiving channel 1 / j, j = 1,2, ..., N, the signal after the analog-to-digital converter 2 operating with a frequency f _S enters the primary RAM 3 of the FIFO type, where the first stage of the gross delay of the signal is carried out.

At the first stage of coarse signal delay, the primary FIFO type 3 RAM provides, up to the signal sampling interval T _S = 1 / f _S, signal delay compensation between the receiving channels 1/1 ... 1 / N of the device signals. For practical applications, the delay in the primary RAM 3 of the FIFO type is of the order of 1024 periods of the clock frequency of the device, equal to the sampling frequency of the ultrasonic signal f _S.

The sequence of samples of the signal {X _i } from the output of the primary RAM 3 of the FIFO type is supplied simultaneously to the inputs of the primary block of the shift registers 4 and the primary filter-interpolator 5.

Using the primary filter-interpolator 5, the first interpolation step is performed, on which the samples of the input signal are formed, delayed by half the sampling interval of the signal, i.e. by 0.5 T _S. As a result of the filtering, at the output of the primary filter of the interpolator 5, a sequence of signal samples {X _{i + 0.5} } is formed.

The primary filter interpolator 5 is non-recursive and uses a symmetric impulse response that satisfies the relation (L. Rabiner, B. Gould. Theory and application of digital signal processing. M: Mir, 1978, p. 93):

where h _m are the values of the impulse response, M is the order of the filter, which is an even number. The use of a symmetrical impulse response makes it possible to halve the number of multipliers in comparison with the standard filter implementation.

The primary block of shift registers 4 is used to align the stream of samples of input data {X _i } with the stream of calculation results {X _{i + 0.5} } of the primary filter interpolator 5 with the aim of simultaneously using them in the secondary filter interpolators 6, 7 in the second interpolation step .

The formation of samples of the input signal delayed by 0.25 T _S is performed using a secondary filter-interpolator 6 by processing the signal samples {X _i } and {X _{i + 0.5} } according to the formula (4):

Accordingly, the input signal is delayed by a fractional delay of 0.75 T _S by the secondary filter-interpolator 7 by processing the signal samples {X _i } and {X _{i + 0.5} } according to formula (5):

Secondary filter interpolators 6, 7 are completely identical, are non-recursive and use, like the primary filter interpolator 5, a symmetrical impulse response. The structures of all filter interpolators are similar. The structural difference between the primary filter-interpolator 5 and the secondary filter-interpolators 6, 7 is the organization of relations between the shear ones due to the fact that in the case of the primary filter-interpolator 5, samples of only one data sequence {X _i } from RAM 3 of the FIFO type, and the inputs of the secondary filter interpolators 6, 7 simultaneously receive samples of two data sequences: a sequence of samples {X _i } from the primary block of shift registers 4 and sequence of samples {X _{i + 05} } from the primary filter-interpolator 5.

After aligning the data flows coming from the primary block of the shift registers 4, the primary filter interpolator 5 and the secondary filter interpolators 6,7 at the outputs of the secondary blocks of the shift registers 8-11, all possible delays of each signal count are simultaneously generated in accordance with the time diagram presented figure 2. Figure 2 presents the data at the output of the secondary block of shift registers 8 (position A), which are samples of the input signal generated immediately after analog-to-digital conversion, and corresponding to zero fractional delay. The signal samples with a fractional delay of 0.5 T _S (position B) at the output of the secondary block of shift registers 9 are formed at the first stage of interpolation from the input signal samples using the primary filter interpolator 5. Signal samples with fractional delays of 0.25 T _S (position B) and 0.75 T _S (position Г) are formed respectively by the secondary filter-interpolator 6 and the secondary filter-interpolator 7 at the second stage of interpolation from the input samples of the signal and the results of the calculation of samples with a fractional delay of 0.5 T _S using the primary filter-interp solitaire 5. Thus, at the inputs of the shapers 12 rays at any time there is a complete set of values of the smooth delays of the signal.

In the analogue of this technical solution, to implement the full set of fractional signal delays, 4M multipliers are required that work with the clock cycle of the DFU (United States Patent 6,695,783, published 24.02.2004). In the claimed utility model, the number of multipliers required to implement the full set of fractional signal delays is 3M / 2, which is approximately 2.7 times less than in its analogue.

In each beamformer 12, when performing dynamic focusing using multiplexer 13, the required value of the smooth signal delay is selected. Then, using the secondary RAM 14 of the FIFO type, the second stage of coarse delay is performed, which is unique for each of the L beams that are simultaneously formed. For practical applications, the delay in the secondary RAM 14 of the FIFO type is about 64 periods of the clock frequency.

To implement the apodization function of the ultrasonic beam, the multiplier 15 performs amplitude weighting of the signal samples.

The combination of signals from various sensor elements entering the receiving channels 1,2, ..., N is carried out using adders 16 channels. Moreover, as shown in Fig. 1, for the formation of each beam, a separate group of channel adders is used so that the data from the output of the i-th adder 16 / i, i = 1,2, ..., L, of each j-th channel, j = 1,2, ..., N-1, go to the input of the i-th adder 16 / i, i = 1,2, ..., L, j + 1 channel. In this case, the resulting signal corresponding to the i-th beam, i = 1,2, ..., L, is formed at the output of the i-th adder of the N-th channel.

In the case of low-frequency sensors, in particular, sensors used in cardiac studies, it is possible to reduce the passband of the receiving path with a corresponding decrease in the sampling frequency of the echo signal. In this case, with a decrease in the sampling frequency of the echo signal, the hardware costs necessary for the formation of a given number of rays will also decrease. As a result, it becomes possible to use the released computing resources to form several additional beams in the processor time separation mode — time multiplexing.

The number of additional receiving beams implemented in the time multiplexing mode depends on the operating frequency of the sensor. If, due to a decrease in the sampling frequency, the computational costs necessary to form one beam are reduced by a factor of P, then it becomes possible to simultaneously form p groups of rays with L rays in each group. In this case, the total number of simultaneously generated rays will be equal to P · L. Suppose, for example, that the sampling frequency of the analog-to-digital converter 2 is selected in such a way that the receiving path of the diagram-forming device is designed for a maximum operating frequency of the sensor of 10 MHz. Then, when using a sensor with an operating frequency of 5 MHz, the signal sampling rate can be reduced by 2 times. Accordingly, with L = 4, the device can provide, due to time multiplexing, the formation of an additional 4 rays.

The formation of acoustic lines using time-division multiplexing is realized by building signal samples to form several lines into a single data stream, followed by processing them on a single computing device. Temporary multiplexing is carried out with a clock frequency of the diagram-forming device. For example, if the device implements the formation of four groups of receiving beams in the time-multiplexing mode, then samples of all four groups of beams with the device clock speed will be sequentially unloaded from the primary RAM 3 of the FIFO type, which performs the function of a coarse signal delay. The timing diagram of the unloading of signal samples from the RAM 3 FIFO for the formation of 4 groups of beams G1-G4 in the time multiplexing mode is shown in Fig.3. In accordance with the time chart shown in Fig. 3, a count for the formation of the first group L of rays G1 is issued in the first clock cycle, a second group of rays G2 in a second clock cycle, a third group of rays G3 in a third clock cycle, and a fourth clock cycle counting of the fourth group of rays G4 (see figure 3). The process is then repeated. Moreover, the data of each group of beams are delayed in the primary RAM 3 of the FIFO type by a different amount of delay in accordance with the implemented focusing.

Further, the formation of the rays is performed on the same computing means of the digram-forming device in the mode of dividing the processor time between the samples of the signal belonging to different groups of rays.

The use of a diagram-forming device for multipath reception of ultrasonic signals in medical diagnostic systems will allow us to create ultrasound devices for visualizing the state of the internal organs of a person, performing accurate diagnostic tests with obtaining images of high diagnostic quality, due to the result achieved in this technical solution, which consists in improving dynamics of ultrasound image formation. In addition, a reduction in hardware costs compared to similar devices will reduce the cost of the product, as well as reduce its dimensions and power consumption, which will allow the device to be used both as a part of stationary and portable ultrasound devices.

Claims (3)

1. Diagram-forming device for multipath reception of ultrasonic signals, containing a receiving and transmitting module, which includes receiving channels of signals from the elements of the ultrasonic sensor, each receiving channel of signals is electrically connected through an individual analog-to-digital converter with primary random access memory of the FIFO type, which in turn, connected to a primary filter-interpolator, as well as containing a secondary random access memory of the FIFO type, multipliers, multiplexers and adders, distinguishing the fact that the primary RAM of the FIFO type is connected to the primary block of shift registers, the outputs of the primary filter interpolator and the primary block of shift registers are connected to the corresponding inputs of two secondary filter interpolators, while the primary block of shift registers, the primary filter interpolator and secondary filters -interpolators are connected through the secondary blocks of the shift registers with the corresponding inputs of the beam shapers, each of which is connected to the corresponding adder of channels and on chaet serially connected multiplexor, the secondary FIFO type memory and a multiplier, in addition, each filter interpolator is an interpolator filter with a symmetric impulse response fixed. 2. The diagram-forming device according to claim 1, characterized in that the electrical connection between the elements of the device is carried out via data buses. 3. The diagram-forming device according to claim 1, characterized in that the number of receiving channels of the signals corresponds to the number of simultaneously used elements of the ultrasonic sensor.