EA023835B1 - Diagram-forming device for multipath reception of ultrasound signals - Google Patents

Abstract

The invention relates to the field of medical device building, in particular to devices for ultrasound echolocation of internal organs and can be used in medical diagnostic systems. The invention ensures reduction of hardware expenses for improvement of dynamics of ultrasound image formation. The device contains receiving-transmitting module, which includes receiving channels of signals from elements of ultrasound sensor. Each receiving channel is electrically connected via individual analogue-digital converter with primary random access memory (RAM) of FIFO type, which in its turn is connected with primary filter-interpolator. Primary RAM of FIFO type is connected with primary unit of shift registers. Outlets of primary filter-interpolator and primary unit of shift registers are connected with respective inlets of two secondary filter-interpolators. Primary unit of shift registers, primary filter-interpolator and secondary filter-interpolators are connected via secondary units of shift registers with respective inlets of beam shapers. Each of beam shaper is connected with respective adder of channels and includes successively connected multiplexor, secondary RAM of FIFO type and multiplier. Each filter-interpolator represents filter-interpolator with fixed symmetric impulse characteristics. In primary filter-interpolator shift registers are combined in one line connected with primary RAM of FIFO type. In secondary filter-interpolator shift registers are combined in two lines, one of which is connected with primary unit of shift registers, and the other one is connected with primary filter-interpolator.

Description

The present invention relates to the field of medical instrumentation, in particular to devices for ultrasonic echolocation of internal organs, and can be used in medical diagnostic systems.

From the current level of technology, a multi-beam ultrasound beam-forming device (DFU) is known to provide a high frame rate of the image being generated, each channel of which includes an analog-to-digital converter (ADC), a signal delay generation module, an apodization module, and adders (ipieb 81a1e5 Ra1ep1 5905692, publ . 05/18/1999). The disadvantage of this technical solution is that when implementing multipath reception, an increase in the number of receiving channels is associated with a proportional increase in the number of filter interpolators and, accordingly, hardware costs, as well as the cost of the device.

Also known from the prior art is a beam-forming device for multipath reception of ultrasonic signals, comprising a receiving-transmitting module, which includes receiving channels of signals from sensor elements, each receiving channel of signals is electrically connected through an individual analog-to-digital converter with primary random access memory of type ΡΙΡΘ, which , in turn, is connected to the filter-interpolator, as well as containing secondary random access memory of type ΡΙΡΘ, multipliers, multiplexers and adders (with ., For example, Ipyeb 81a1e8 Ra! En! 6695783, publ. 24.02.2004).

In this technical solution, an increase in the number of receiving channels does not lead to a proportional increase in the number of filter interpolators. However, the disadvantage of this device is the excessive hardware costs for generating interpolated signal samples, since the implemented generation of interpolated signal samples does not take into account the fact that when implementing a fractional signal delay equal to 0.5 of the sampling interval, the number of multipliers due to the use of the symmetrical impulse response of the filter-interpolator can be reduced twice, as well as the fact that there is no need to perform computational operations when the fractional delay nala is zero. The disadvantage is also the excessive hardware costs associated with the need for constant adjustment of the coefficients of the filter-interpolator with the cycle of arrival of the signal samples.

The task to which the claimed technical solution is directed is to reduce hardware costs to improve the dynamics of the formation of ultrasound images.

This problem is solved due to the fact that in the claimed diagram-forming device for multipath reception of ultrasonic signals, containing a receiving-transmitting module, which includes receiving signal channels from the sensor elements, each signal receiving channel is electrically connected through an individual analog-to-digital converter with a primary operational memory of type ΡΙΡΘ, which, in turn, is connected to the primary filter-interpolator, as well as containing secondary random access memory of type ΡΙΡΟ, multipliers, multiplexers and adders, according to the invention, the primary memory of type ΡΙΡΟ is connected to the primary block of shift registers, the outputs of the primary filter interpolator and the primary block of shift registers are connected to the corresponding inputs of two secondary filter interpolators, while the primary block of shift registers, the primary filter interpolator and secondary filter interpolators are connected through secondary blocks of the shift registers with the corresponding inputs of the beam shapers, each of which is connected to the corresponding channel adder and includes a series-connected multiplexer, a secondary memory of type ΡΙΡΟ and a multiplier, in addition, each filter interpolator is a filter interpolator with a fixed symmetrical impulse response and includes interconnected shift registers, intermediate adders, multipliers and a common adder, at the same time, in the primary filter interpolator, the shift registers are combined in one row connected to the primary memory of type типа, and in the secondary In the filter interpolator, the shift registers are combined in two rows, one of which is connected to the primary block of the shift registers, and the other to the primary filter interpolator.

The electrical connection between the elements of the device can be made via data buses.

The number of receiving channels of the signals may correspond to the number of simultaneously used elements of the ultrasonic sensor.

The technical result provided by the given set of features is to reduce hardware costs to increase the frame rate, which affects the improvement of the dynamics of the formation of ultrasound images due to the structural design of the entire device, in particular due to the fact that each filter interpolator is a filter interpolator with a fixed symmetrical impulse response, moreover, in the primary filter-interpolator, the shift registers are combined in one row connected to the primary opera ativnost memory type ΡΙΡΟ, a secondary filter-interpolator shift registers are combined in two rows, one of which is coupled to the primary block of shift registers, and the other - with a primary-filter interpolator.

Thus, a full load of computing means of filter interpolators is provided.

- 1 023835 due to the organization of the computational process so that at any time the filterinterpolator is used only to form a fractional delay and is not idle when it is not necessary to form a fractional delay of the signal. In addition, the use of filter interpolators with a fixed symmetrical impulse response allows you to halve the number of multipliers, and also, since, in contrast to the analogue in the calculation process, filter interpolators do not change their impulse response, it is possible to use a simplified structure of multipliers that implement the operation multiplications in the structure of the filter-interpolator only by a fixed coefficient.

The essence of the claimed device is illustrated by drawings that do not cover and, moreover, do not limit the scope of claims for this decision, but are only illustrative materials of a particular case of the device. The drawings show:

in FIG. 1 is a block diagram of a device;

in FIG. 2 is a block diagram of an 8th order filter interpolator for performing a first interpolation step;

in FIG. 3 is a block diagram of an 8th order filter interpolator for performing a second interpolation step;

in FIG. 4 is a timing chart for generating smooth signal delay results;

in FIG. 5 is a timing diagram of the operation of the device in the additional beamforming mode by time multiplexing.

The device includes a transmit-receive module, which includes N receive channels of signals 1/1 ... 1 / Ν in accordance with the number of simultaneously used sensor elements.

Each receiving channel of the signals 1 / f _) = 1, 2, ..., N is electrically connected through an individual analog-to-digital converter 2 to the primary RAM 3 of the PRO type. Primary random access memory 3 of type P1PO is connected to the primary block of shift registers 4 and to the primary filter interpolator 5. The outputs of the primary filter interpolator 5 and to the primary block of shift registers 4 are connected to the corresponding inputs of two secondary filter interpolators 6, 7. The primary block of shift registers 4, the primary filter interpolator 5 and the secondary filters interpolators 6, 7 are connected through the corresponding secondary blocks of the shift registers 8, 9, 10, 11 with the corresponding inputs of the beam shapers 12. Each beamformer 12 includes a series-connected multiplexer 13, a secondary random access memory 14 of the type P1PO and a multiplier 15 and is connected to a corresponding adder 16 channels. The number b of the shapers 12 rays is equal to the number b of adders 16 channels, i.e. for b beam shapers 12/1 ... 12 / b, b channel adders 16/1 ... 16 / b are used.

Each filter interpolator is a filter interpolator with a fixed symmetrical impulse response. Each filter interpolator 5, 6, 7 includes interconnected shift registers 17, intermediate adders 18, multipliers 19, and a common adder 20. Moreover, each filter M-order interpolator 5, 6, 7 contains shift registers 17/1. .. 17 / M, adders 18/1 ... 18 / (M / 2), multipliers 19/1 ... 19 / (M / 2) and adder 20. In the primary filter interpolator 5, the shift registers 17 are combined in one row connected to the primary RAM 3 type P1RO. In the secondary filters-interpolators 6, 7, the shift registers 17 are combined in two rows, one of which is connected to the primary block of the shift registers 4, and the other to the primary filter-interpolator 5.

The device provides multipath reception of an ultrasonic signal based on the dynamic tuning of the signal delay system represented by a sequence of digital data. In this case, coarse tuning of the signal delay up to the sampling step of the input signal is carried out on the basis of using primary and secondary random access memory 3, 14 of the Р1РО type, and a smooth (fractional) delay with higher accuracy than the signal sampling step is performed using the primary and secondary filter interpolators 5, 6, 7. The primary and secondary filters interpolators 5, 6, 7 form all possible smooth signal delays, which are then used to form all receiving beams. The transmitting and receiving module is made mainly in the form of a housing.

According to the results of many studies (IpKey 81a1e5 Ra1ep1 6695783, published February 24, 2004), it is believed that the minimum step of changing the signal delay, a further decrease of which will not lead to a noticeable increase in the quality of the image formed, is 1 / (16 £ _s ), where £ _{with the} operating frequency of the sensor. In this case, the interpolation coefficient K is given by

K = 16G / G ₃ , (1) where £ § is the sampling frequency of the ultrasonic signal.

If the operating frequency of the sensor £ _s does not exceed 12.5 MHz, which corresponds to the overwhelming number of practical applications, then, as follows from formula (1), with an ultrasonic signal sampling frequency of £ ₃ = 50 MHz, it is sufficient that the interpolation coefficient K be equal to 4. In this case, the filter interpolator should provide a signal delay in increments of 0.25T ₃ , where T ₃ = 1 / £ ₃ the sampling rate of the ultrasonic signal, i.e. form a set of fractional signal delays: 0.25Т ₃ ,

- 2 023835

0.5T ₃ , 0.75T ₃ .

The interpolation coefficient K, equal to 4, can also be used for ultrasonic sensors with a higher operating frequency by increasing the speed of the ADC. For example, if you use ultrasonic sensors with a maximum operating frequency of 15 MHz, then for K = 4 it is enough for the ADC to provide a signal sampling frequency of £ ₃ = 60 MHz.

The device operates as follows. In accordance with the block diagram of FIG. 1 in each receiving channel 1 /),.) = 1, 2, ..., N, the signal after the analog-to-digital converter 2, operating at a frequency of Г ₈ , enters the primary random access memory 3 of type ΡΙΡΘ, where the first stage of the gross delay is performed signal.

At the first stage of coarse signal delay, the primary memory of type 3 ΡΙΡΘ provides, up to a sampling interval of the signal T ₈ = 1 / £ _3, compensation for the signal delay between the receiving channels 1/1 ... 1 / Ν of the device signals. For practical applications, the delay in the primary memory of type 3 ΡΙΡΘ is about 1024 periods of the clock frequency of the device, equal to the sampling frequency of the ultrasonic signal C

The sequence of samples of the signal {X ₁ } from the output of the primary RAM 3 of type ΡΙΡΟ is supplied simultaneously to the inputs of the primary block of the shift registers 4 and the primary filter of the interpolator 5.

Using the primary filter-interpolator 5, the first interpolation step is performed, on which the samples of the input signal are formed, delayed by half the sampling interval of the signal, i.e. by the value of 0.5T ₃ . As a result of filtering at the output of the primary filter of the interpolator 5, a sequence of samples of the signal {X _{1 + 0} , ₅ } is formed.

The primary filter interpolator 5 is non-recursive and uses a symmetrical impulse response that satisfies the relation (L. Rabiner, B. Gould. Theory and application of digital signal processing. M: Mir, 1978, p. 93) th _t = ym-sh + 1 , t = 1, 2, ..., M, (2) where th _t are the values of the impulse response;

M is the order of the filter, which is an even number.

The use of a symmetrical impulse response makes it possible to halve the number of multipliers in comparison with the standard filter implementation.

An embodiment of a filter interpolator 5 with a symmetrical impulse response for filter order M = 8 is shown in FIG. 2. The calculations in the filter-interpolator 5 are made according to the formula

AG / 2 = ™ = ΜΙ2.Μ / 2 +1, ... (3) t-1

Partial sums (see the right side of expression (3)) before performing the multiplication operations are implemented using adders 18/1 ... 18 / (M / 2), and the multiplication operation by filter coefficients {'1'ι, 1ι ₂ , ... , th _{m / 2} } - using the multipliers 19/1 ... 19 / (M / 2). Since each multiplier performs multiplication only by a fixed number in the calculation process, it can be implemented according to a simplified scheme with strict logic of work or a tabular method. When constructing DFU using FPGAs (programmable integrated logic circuits), this approach allows us to reduce the number of logical elements needed to implement multiplication operations. The final filtering result is formed at the output of the adder 20.

The primary block of shift registers 4 is used to align the stream of samples of the input data {X ₁ } with the stream of calculation results {Χι + ₀ . ₅ } of the primary filter-interpolator 5 for the purpose of their simultaneous use in the secondary filter-interpolators 6, 7 at the second stage of interpolation.

The formation of samples of the input signal, delayed by 0.25 T ₈ , is performed using a secondary filter-interpolator 6 by processing the signal samples {X ₁ } and {X _{1 + 115} } according to the formula (4)

Λ // 4

30 + 0.25 ⁼ Ά, -Χ t / 1 Τ X, '+ yes-1-0.5) + ^ 2t (Xΐ, t + Χί-> η + 0.5)] (4) t = 1

Accordingly, the delay of the input signal by a fractional delay of 0.75 T ₃ is performed by the secondary filter-interpolator 7 by processing the signal samples {CD and {X _{1 + 0} . ₅ } by the formula (5)

Λ // 4

- ^ / + 0.75 = Σ [^ ΓΗ-ΐί ^ ι-ζΗ + Ι + Ο.δ + Л + т) ⁺ ^ 2ш (^ (+ т + 0.5 + Л-т + 1)] СО т = \

Secondary filter interpolators 6, 7 are completely identical, are non-recursive and use, like the primary filter interpolator 5, a symmetrical impulse response. In this case, a block diagram of each of the filter interpolators 6, 7 shown in FIG. 3 is similar to the block diagram of the filter-interpolator 5 shown in FIG. 2. Structures of all filter interpolators

- 3 023835 are similar. The structural difference between the primary filter-interpolator 5 and the secondary filter-interpolators 6, 7 is the organization of relations between the shear ones due to the fact that, in the case of the primary filter-interpolator 5, samples of only one sequence of data {X ₁ } from the primary RAM 3 type missile, and the inputs of the secondary filter interpolators-6, 7 arrive simultaneously samples two data sequences: sequence samples {x _1} from the primary shear block Registers 4 and sequence samples {x _{1 + 0. 5} } from the primary filter interpolator 5.

After aligning the data flows coming from the primary block of the shift registers 4, the primary filter interpolator 5 and the secondary filter interpolators 6, 7 at the outputs of the secondary blocks of the shift registers 8-11, all possible delays of each signal count are simultaneously generated in accordance with the time diagram presented in FIG. 4. In FIG. 4 shows the data at the output of the secondary block of shift registers 8 (position A), which are samples of the input signal generated immediately after analog-to-digital conversion, and corresponding to zero fractional delay. The signal samples with a fractional delay of 0.5 T ₈ (position B) at the output of the secondary block of shift registers 9 are generated at the first stage of interpolation from the input signal samples using the primary filter interpolator 5. Signal samples with fractional delays 0.25 T ₃ (position B) and 0.75 T ₃ (position D) respectively formed secondary filtrominterpolyatorom filtrominterpolyatorom 6 and secondary 7 at the second stage of interpolation of the input signal samples and the results of calculation with a fractional sample delay ₃ 0.5 T with a primary filter inte polyatora 5. Thus, at the inputs of generators 12 rays at any point in time there is a complete set of delays smooth signal values.

In an analogue of the invention, to implement the full set of fractional signal delays, 4M multipliers are required, operating with a clock cycle of DFU (IIKeb 31a1s5 Ra1ei1 6695783, publ. 02.24.2004). In the claimed invention, the number of multipliers required to implement the full set of fractional signal delays is 3M / 2, which is approximately 2.7 times less than in the analogue of the invention.

In each beamformer 12, when performing dynamic focusing using multiplexer 13, the required value of the smooth signal delay is selected. Then, using the secondary random access memory 14 of the P1PO type, the second stage of gross delay is carried out, which is unique for each of the b simultaneously generated beams. For practical applications, the delay in the secondary RAM 14 of type P1PO is of the order of 64 periods of the clock frequency.

To implement the function of apodization of the ultrasonic beam, the multiplier 15 performs amplitude weighting of the signal samples.

The combination of signals from various sensor elements entering the receiving channels 1, 2, ..., Ν is performed using adders of 16 channels. Moreover, as shown in FIG. 1, for the formation of each beam, a separate group of channel adders is used so that the data from the output of this adder 16 / ί, ί = 1, 2, ..., b, of each _) channel, _) = 1, 2, ..., Ν-1, go to the input of the ί-th adder 16 / ϊ, 1 = 1,2, ..., b, | + of the 1st channel. In this case, the resulting signal corresponding to the ί -th beam, ί = 1, 2, ..., b, is formed at the output of the го-th adder of the Ν-th channel.

In the case of low-frequency sensors, in particular, sensors used in cardiac studies, it is possible to reduce the passband of the receiving path with a corresponding decrease in the sampling frequency of the echo signal. In this case, with a decrease in the sampling frequency of the echo signal, the hardware costs necessary for the formation of a given number of rays will also decrease. As a result, it becomes possible to use the released computing resources to form several additional beams in the processor time separation mode — time multiplexing.

The number of additional receiving beams implemented in the time multiplexing mode depends on the operating frequency of the sensor. If, due to a decrease in the sampling frequency, the computational costs necessary for the formation of one beam are reduced by a factor of P, then it becomes possible to simultaneously form P groups of rays with L rays in each group. In this case, the total number of simultaneously formed rays will be equal to Pb. Suppose, for example, that the sampling frequency of the analog-to-digital converter 2 is selected so that the receiving path of the beam-forming device is designed for a maximum operating frequency of the sensor of 10 MHz. Then, when using a sensor with an operating frequency of 5 MHz, the signal sampling rate can be reduced by 2 times. Accordingly, with b = 4, the device can provide the formation of an additional 4 rays due to time multiplexing.

The formation of acoustic lines using time-division multiplexing is implemented by building signal samples to form several lines into a single data stream, followed by processing them on a single computing device. Temporary multiplexing is carried out with a clock frequency of operation of the beamforming device. For example, if a device implements the formation of four groups of receiving beams in the time-multiplexing mode, then samples of all four groups of beams with a clock speed of the device will be sequentially unloaded from the primary RAM 3 of the Р1РО type, which performs the function of a coarse delay of the signal. The timing diagram of the unloading of signal samples from the primary memory 3 of the PRO type to form 4 groups of rays 01-04 in the time multiplexing mode is shown in FIG. 5. In accordance with the timing diagram of FIG. 5, a count for the formation of the first group of rays 01, in a second clock — a count of the second ray 02, a third clock — a count of the third ray 03, and a fourth clock — a count of the fourth ray 04 (see Fig. 5). 5). The process is then repeated. Moreover, the data of each group of beams are delayed in the primary RAM 3 of the P1RO type by a different amount of delay in accordance with the implemented focusing.

Further, the formation of the rays is performed on the same computing means of the digram-forming device in the mode of dividing the processor time between the samples of the signal belonging to different groups of rays.

The use of a diagram-forming device for multipath reception of ultrasonic signals in medical diagnostic systems will allow us to create ultrasound devices for visualizing the state of the internal organs of a person, performing accurate diagnostic tests with obtaining images of high diagnostic quality, due to the result achieved in this technical solution, which consists in improving the dynamics of formation ultrasound image. In addition, reducing hardware costs compared to analog devices will reduce the cost of the product, as well as reduce its size and power consumption, which will allow the device to be used both as a part of stationary and portable ultrasound devices.

Claims (3)

CLAIM 1. Diagram-forming device for multipath reception of ultrasonic signals, comprising a receiving and transmitting module, which includes receiving channels of signals from the elements of the ultrasonic sensor, each receiving channel of signals is electrically connected through an individual analog-to-digital converter with primary random access memory of the Р1РО type, which, in in turn, it is connected to the primary filter-interpolator, as well as containing secondary random access memory of the P1RO type, multipliers, multiplexers and adders, excellent in that the primary RAM of the P1PO type is connected to the primary block of shift registers, the outputs of the primary filter interpolator and the primary block of shift registers are connected to the corresponding inputs of two secondary filter interpolators, while the primary block of shift registers, the primary filter interpolator, and secondary filters -interpolators are connected through the secondary blocks of the shift registers with the corresponding inputs of the beam shapers, each of which is connected to the corresponding adder channels and includes a series-connected multiplexer, a secondary random access memory of the Р1РО type and a multiplier, in addition, each filter interpolator is a filter interpolator with a fixed symmetrical impulse response and includes interconnected shift registers, intermediate adders, multipliers and a common adder, while in the primary filter -interpolator shift registers are combined in one row, connected to the primary random access memory of type Р1РО, and in the secondary filter-interpolator shift Registers are combined in two rows, one of which is coupled to the primary block of shift registers, and the other - with a primary-filter interpolator. 2. The diagram-forming device according to claim 1, characterized in that the electrical connection between the elements of the device is carried out via data buses. 3. The diagram-forming device according to claim 1, characterized in that the number of receiving signal channels corresponds to the number of simultaneously used elements of the ultrasonic sensor.