JP3024129B2 - High-speed FIR echo canceller - Google Patents

Description

The present invention relates to an FIR type echo canceller, and more particularly to an FIR type echo canceller.
The present invention relates to an acoustic echo canceller having a large filter order.

(Prior Art) An acoustic echo canceller aims at eliminating echo due to acoustic coupling from a speaker to a microphone. In this acoustic coupling, the reverberation time is several hundred milliseconds and the FI
When an echo canceller is configured with an R-type filter, its order is on the order of thousands. Further, since the transmission band is desired to be wider than the telephone line in terms of communication quality, the sampling period is shortened, and the operation speed is extremely high.

Conventionally, to realize such a large-order FIR echo canceller, the order of the FIR filter is divided and
The operation speed was reduced by parallelizing the operation circuits.

(Problems to be Solved by the Invention) However, parallelization of arithmetic circuits by division naturally leads to an increase in circuit scale, and it has been difficult to realize an acoustic echo canceller with a practical circuit scale.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an echo canceller having a smaller circuit scale and a reduced amount of calculation.

(Means for Solving the Problems) The high-speed FIR echo canceller according to the present invention performs a block processing of M × N-order by performing block processing for each M samples from a reception signal and a transmission signal of continuous M samples (M is an integer of 2 or more). (N is an arbitrary natural number) FIR type echo canceller of less than M ² N-order FIR filters, a reception signal synthesis circuit for synthesizing an input signal to the FIR filter from the reception signals of M samples, and the FIR A pseudo echo synthesis circuit for synthesizing pseudo echoes of M samples continuous from the output of the filter;
M subtraction circuits for subtracting the pseudo echo from the M samples of the transmission signal to obtain a residual output signal of each sample, and modifying coefficients of the FIR filter so that the error signal is smaller than the residual output signal. A correction amount calculation circuit for obtaining the amount, and a coefficient correction circuit for correcting the coefficient of the FIR filter based on the correction amount, the filter coefficient output from the FIR filter, and the correction signal.

(Operation) First, the operation of the present invention will be described for the simplest case, in which the received signal and the transmission signal are 2 × N echo cancellers each having two samples (M = 2). In a generally used echo canceller of the block LMS method, a pseudo echo (i), a residual signal e (j) and an estimated impulse response hj are obtained according to the following equations.

_{However, x 2j = (x (2j} ), x (2j-1), ..., x (2j-2N + 1)) T h 2j = (h 2j (0), h 2j (1), ..., h 2j (2N -1)) ^{T at} the upper right of the T matrix represents transpose.

Here, x (i), y (j), (i) and e (i) are a received signal, a transmitted signal, a pseudo echo signal and a residual output signal at time i, respectively, and h ^2j (k) (k = 0, 1, 2, ... 2N-1) is the estimated impulse response at time 2j, and μ is a coefficient that determines the convergence speed. The multiplication in this method is (1), (2)
Equations require 2N times each and equation (5) requires 4N times, for a total of 8N times.

Next, in order to explain the principle of this patent, the following four vectors are defined. _XEj = (x (2j), x (2j-2),..., X (2j−2N + 2)) ^T x _Oj = (x (2j-1), x (2j-3), ..., x (2j-2N + 1)) T h Ej = (h 2j (0), h 2j (2), ..., h 2j (2N-2) ^{_{) T h Oj = (h 2j}} (1), h 2j (3), ..., with h ^2j (2N-1)) ^T this definition (1), rewritten in the form of matrix (2) , Becomes Here, in general, the following equations can be modified in the n × m matrices A, B, and C and the m × matrices D and E.

However, the unit matrix of In: n × n On: n × n zero matrix In this case, the required multiplication number is 4 nmm on the left side, but 3 nmm on the right side, and is 25%. Has been reduced. By applying equation (7) to the right side of equation (6), Becomes To further reduce the number of additions, if the following signals and their vectors are defined, r ₁ (j) = x (2j) −x (2j−1) (9) r ₂ (j) = x (2j−1) ) (10) r ₃ (j) = x (2j−2) −x (2j−1) (11) r _1j = (r ₁ (j), r ₁ (j−1),..., R ₁ (j) _{^{-N + 1)) T r 2j}} = (r 2 (j), r 2 (j-1), ..., r 2 (j-N + 1)) T r 3j = (r 3 (j), r 3 (j-1 ),..., R ₃ (j−N + 1)) ^T (8) Becomes Similarly, by transforming equation (5) with x _Oj , x _Ej , h _Oj , h _Ej and applying equation (7), Becomes From the above, when the calculation is performed using the equations (9) to (13) instead of the equations (1), (2), and (5), the number of multiplications is 6N, which is 8N times in the conventional block LMS method. This is a 25% reduction.

Next, 2 ^m · 2 is used to process M = 2 ^m samples in a block.
The N-order echo canceller will be described. First, in the conventional block LMS method, the pseudo echo (j) and the residual signal e
(J) and estimated impulse response hj Is required. Here, if (i) is divided into two consecutive samples, the same modification as that of M = 2 is possible.
25% reduction. Further, equation (12) is an FIR with r _ij as input.
Since the filter is used as a filter, the deformation by the equation (7) can be repeated again. After all, the number of multiplications is reduced to (3/4) ^m by applying m times.

More generally, for any M, M = a ₁ ^b1 · a ₂ ^b1 ·
… · A ₁ ^bi ·… a _s ^bs (a _i : prime number, b _i : natural number). Therefore, a reduction method similar to the above-described method can be applied to each prime a _i . _By repeating _i times, the number of times of multiplication can be reduced.

Further in the present invention In other words, the number of times of multiplication can be similarly reduced by the block learning identification method. As described above, in multiplication with a symmetric matrix, the number of multiplications in an echo canceller in block processing is reduced by applying the fact that the total number of multiplications can be reduced by a combination of addition and subtraction.

(Embodiment) FIG. 1 shows a first embodiment of the present invention. This is because M =
In the case of 2 ^m, successive 2 ^m samples of the received signal x (j),
.., X (j−2 ^m +1), the received signal synthesizing circuit 10 generates 3 ^m synthesized signals. The output of the received signal synthesis circuit 10 is 3 ^m
Are input to the FIR filters 20, 21,. Further, the pseudo echo synthesis circuit 30 synthesizes a continuous pseudo echo signal of 2 ^m samples from the outputs of the FIR filters 20, 21,. The combined pseudo echo signal (j) of each sample is subtracted from the transmission signal y (j) of each sample to generate a residual output e (j). Next, a convergence coefficient μ is applied to each residual output by the correction amount calculation circuit 50.
Is multiplied to obtain each correction amount. Finally, the coefficient correction circuit 60 corrects the filter coefficient of the FIR filter according to the equation (16) based on the correction amount.

Here, the reception signal synthesis circuit and the pseudo echo synthesis circuit will be described in detail. First, as shown in FIG. 2, the received signal synthesizing circuit 10 can be configured by combining the unit received signal synthesizing circuits 11 for performing the calculations shown in the equations (9) to (11). For the received signal of continuous 2 ^m samples, the first ⁽ 2 ^(m-1)) unit received signal synthesizing circuits 11 in the first stage form a synthesized signal from adjacent signals and send it to the second stage. That is, the unit reception signal synthesis circuit 11 performs (9)
(3) to output three synthesized signals.
In the second stage, the next ⁽ 2 ^{) (m-1)} received signal synthesizing circuits 11 synthesize the next synthesized signal from the outputs of the adjacent synthesizing circuits. By repeating this, the output of the last m-th stage is (r ₁ (j), r ₂ (j), r ₃ j) to (r) as shown in FIG.
_{^{3 m -2 (j), r}} 3 m -1 j), 3 m pieces of composite signal r ₃ ^m (j)) is represented. Next, as shown in FIG. 3, the pseudo echo combining circuit 30 can be configured by combining a unit pseudo echo combining circuit 31 for adding the matrix of the equation (8). This is because the output of the 3 ^m FIR filters is opposite to that of the reception signal synthesis circuit, and the 3 ^(m-1) pseudo echo synthesis circuits 31 in the first stage are configured as 2 · 3 ^(m −3) by three consecutive outputs. ¹⁾ Create one composite signal. That is, two pseudo echo signals are output by performing calculations based on equation (8) from three input signals. If this is repeated m times,
Finally, a pseudo echo signal of 2 ^m continuous samples is output.

Next, FIG. 4 shows a detailed block diagram when M = 2 as a more specific embodiment of the present invention.

Received signal synthesis circuit from received signals x (2j), x (2j-1)
In 11, the subtraction circuits 400 and 401 and the two-sample time delay circuit 90
, The input r ₁ (j), r of each FIR filter 20,21,22
Calculate ₂ (j), r ₃ (j) In each filter, the same configuration
₁ ^j (i), h ₂ ^j (i), h ₃ ^j (i) and r of the input register 71
_{1 (j-i), r} 2 (j-i), r 3 (j-i) is convolved with product circuit 80 convolution output of the filter f ₁ (j), f
₂ (j) and f ₃ (j) are obtained.

From the output of the filter, the pseudo echo synthesis circuit 31 uses the addition circuits 200 and 201 to generate pseudo echo signals (2j) and (2j−2).
Find 1).

From the transmission signals y (2j) and y (2j-1), a pseudo echo (2
j) and (2j-1) are subtracted by subtraction circuits 402 and 403 to obtain a residual signal. And

Multiplying circuits 300 and 301 multiply the residual signals e (2j) and e (2j-1) by the contents of the constant register 100 to correct the amount. And

The correction amount is calculated by a coefficient correction circuit 61 comprising addition circuits 202 to 207 and multiplication circuits 302 to 304. A coefficient ^{_{h 1 j (i) ~h 3}} j (i) is modified.

(Effect of the Invention) The method according to the present invention can reduce the multiplication circuit by 25% or more,
The effect is further increased by increasing the number of samples M. For this reason, an FIR type echo canceller can be realized with a smaller circuit scale than the conventional method.

[Brief description of the drawings]

FIG. 1 shows a first embodiment according to the present invention. FIG. 2 is a detailed diagram of the received signal combining circuit of the first embodiment. FIG. 3 is a detailed diagram of the pseudo echo combining circuit of the first embodiment.
FIG. 4 is a detailed block diagram when M = 2. In the figure, 10,11 ... received signal synthesis circuit 20,21,22 ... N tap FIR filter 30,31 ... pseudo echo synthesis circuit 40,41 ... M subtraction circuits 50,51 ... correction amount Calculation circuit 60, 61 Coefficient correction circuit 70, 71 N-tap register 80 Convolution product circuit 90 Two-sample time delay circuit 100 Constant register 200-209 Addition circuit 300-304 Multiplication circuits 400 to 403: Subtraction circuits.

Claims (1)

(57) [Claims] 1. A series of M samples (M is an integer of 2 or more)
Of M × N order to block processing for each of the M samples from the received and transmitted signals (N is an arbitrary natural number) in the FIR type echo canceller, M and less than ^two N-th order FIR filter, the reception of M samples A reception signal synthesis circuit that synthesizes an input signal to the FIR filter from a signal; a pseudo echo synthesis circuit that synthesizes a continuous M sample pseudo echo from the output of the FIR filter; and a pseudo echo from the M sample transmission signal. M subtraction circuits for subtracting the residual output signal of each sample to obtain a residual output signal; a correction amount calculation circuit for determining a correction amount of a coefficient of the FIR filter so as to make the error signal smaller than the residual output signal; wherein the filter coefficients and the corrected signal is output correction amount from the FIR filter and a coefficient correction circuit for correcting the coefficients of the FIR filter, M = 2 ^{m (m} is a natural If the received signal combining circuit) is a 3 ^m-number of combined signal from the two inputs 3 and an output unit receiving combining circuit preceding adjacent signal is input is m-stage connected 2 ^m received signals This unit receiving and combining circuit has 2 ^(m-1) units at the first stage,
The second stage is composed of 3 · 2 ^(m−1) ..., The mth stage is composed of 3 ^(m−1) , and each unit received signal combining circuit has two input signals x (2j), x
From (2j−1), r ₁ (j) = x (2j) · x (2j−1) r ₂ (j) = x (2j−1) r ₃ (j) = x (2j−1) · x (2j-1), wherein the pseudo-echo synthesis circuit is a m-stage unit pseudo-echo synthesis circuit having three inputs and two outputs and receiving three adjacent signals at the preceding stage. ^m pieces of said the output of the FIR filter by combining the 2 ^m pieces of the pseudo echo signal is configured to output, the unit pseudo echo combining circuit, the first stage 3
^(m-1) , the second stage is composed of 2.3 ^(m-1) , and the m-th stage is composed of 2 ^(m-1) . Each unit pseudo echo combining circuit has three input f _1. , y a f _2, f ₃ as two pseudo echo signal _{(2j) = f 1 (j} ) + f 2 (j) y (2j-1) = f 2 (j) + f 3 means for calculating the (j) A high-speed FIR echo canceller characterized by having: