JPH0454524Y2 - - Google Patents

Description

[Detailed Description of the Invention] <<Industrial Field of Application>> The present invention relates to improving the arithmetic accuracy of a fixed-point arithmetic unit.

[Conventional technology] Conventionally, fixed-point FFT (Fast Fourier
When calculating a Fast Fourier Transform (Transform), a method called block floating is used. This is a calculation method that assigns one exponent to the data at N points, and scales all N points to 1/2 or 1/4 in advance to prevent overflow.

<<Problem to be solved by the invention>> However, since scaling is always performed by checking the maximum value, points having small values are scaled excessively, resulting in a drop in accuracy. To prevent this, there is a method in which all points have an exponent, that is, a full floating method, but this method has the drawback of making calculations difficult.

The present invention was devised to solve the above-mentioned problems, and an object of the present invention is to realize an arithmetic device using a block floating method that can suppress a decrease in accuracy due to scaling.

<Means for Solving the Problems> The arithmetic device according to the present invention includes a first waveform generating means for generating a signal component having a large amplitude included in an input signal, and a first waveform generating means for generating a signal component having a large amplitude from the input signal. a subtraction means for subtracting the output, an FFT calculation means for inputting the output of the subtraction means, a second waveform generation means for generating a signal on the frequency axis corresponding to the signal component, and an output of the second waveform generation means. and said
It is characterized by comprising an addition means for adding the output of the FFT calculation means.

"Example" The present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of an FFT calculation device according to the present invention. 1 is an A/D conversion circuit to which an analog input signal is connected; 2 is a memory that constitutes a first waveform generating means and generates a signal on the time axis corresponding to a frequency component with a large amplitude included in the input signal; 3; is this memory 2 and A/D
An arithmetic circuit to which the output of the conversion circuit 1 is input; 4 is an FFT arithmetic circuit to which the output of the arithmetic circuit 3 is input; 5
6 constitutes a second waveform generating means and generates a signal on the frequency axis corresponding to the frequency component;
is an addition circuit that adds the output of this memory 5 and the output of the FFT calculation circuit 4.

The operation of the FFT arithmetic device configured as described above will be explained next. Analog signal Si is A/D conversion circuit 1
is converted into a digital signal C ₁ (hereinafter Ci represents a digital signal). If the waveform properties of the input signal Si are known to some extent or are stable, the signal waveform that is the same as the large amplitude frequency component, that is, the peak component included in the input signal Si, is stored in the memory 2 on the time axis. It is written in advance as a synchronized waveform. The previous waveform or a waveform generated by a processor or the like is used for writing. In addition, the waveform on the frequency axis (that is, the Fourier transform of the contents of memory 2) is stored in memory 5,
However, the real part and the imaginary part) are written by a processor or the like. Subtractor 3 is A/D conversion circuit 1
The output C ₂ of the memory 2 is subtracted from the output C ₁ of the memory 2 to output a signal C ₃ without peak components. The FFT calculation circuit 4 receives this signal _C3 and performs FFT calculation using a block floating method. The adding circuit 6 is
FFT calculation result output C ₄ and memory 5 output C ₅
(real part and imaginary part of each) are added, and the final
Outputs the FFT operation result as signal _C0 .

According to the FFT calculation device with such a configuration,
Since the signal C ₃ input to the FFT calculation circuit 4 can have a small ratio between the data peak value and the RMS value, it is possible to suppress a decrease in accuracy due to scaling.

Note that the same applies to the case where a direct current is included as a peak component in the above embodiment. Also, not only when one frequency is included as a peak component,
Similar calculations can be performed even when multiple frequencies are included. That is, it is sufficient to calculate a composite sine wave and set it in the memory 2.

Further, normally, the peak component included in the input signal and the output signal waveform of the memory 2 do not have to be exactly the same.

The same applies when there is a peak (peak value) in the time axis waveform. However, when subtracting a complex waveform as a peak component, it is necessary to calculate its Fourier transform value with high precision and set it in the memory 5.

Furthermore, it is not necessary to use memories as the two waveform generating means, and any waveform generating means can be used. In particular, when a sine wave is used as the peak component, there is almost no need to use a memory as the second waveform generating means.

Further, although the above embodiment shows the case of an FFT calculation device, a frequency signal is input, an IFFT (Inverse FFT) calculation circuit is used in place of the FFT calculation circuit 4, and the first signal generating means is used to generate signals on the frequency axis. By generating a signal on the time axis with the second signal generator, it is possible to realize an IFFT device that suppresses deterioration in accuracy.

《Effect of the invention》 As mentioned above, according to the present invention, the block
By using the floating method, it is possible to realize an arithmetic device with a simple configuration that can suppress a decrease in accuracy due to scaling.

[Brief explanation of the drawing]

The figure is a configuration block diagram showing an embodiment of the arithmetic device according to the present invention. 2...First waveform generating means, 3...Calculating means,
4...Calculating means, 5...Second waveform generating means, 6
...Addition means, Si...Input signal.

Claims (1)

[Claims for Utility Model Registration] (1) A first waveform generating means for generating a signal component with a large amplitude included in an input signal, and a subtracting means for subtracting the output of the first waveform generating means from the input signal; Enter the output of this subtraction means
an FFT calculation means, a second waveform generation means for generating a signal on the frequency axis corresponding to the signal component, an output of the second waveform generation means and the FFT calculation means;
1. An arithmetic device comprising an addition means for adding the output of the arithmetic means. (2) The arithmetic device according to claim 1, wherein the FFT arithmetic means is an IFFT arithmetic means, and the second signal generating means generates a signal on the time axis.