JPH05327511A - Digital/analog converter - Google Patents

Digital/analog converter

Info

Publication number
JPH05327511A
JPH05327511A JP13330792A JP13330792A JPH05327511A JP H05327511 A JPH05327511 A JP H05327511A JP 13330792 A JP13330792 A JP 13330792A JP 13330792 A JP13330792 A JP 13330792A JP H05327511 A JPH05327511 A JP H05327511A
Authority
JP
Japan
Prior art keywords
pulse width
pulse
signal
digital input
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13330792A
Other languages
Japanese (ja)
Inventor
Tomihiko Fukumoto
富彦 福本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13330792A priority Critical patent/JPH05327511A/en
Publication of JPH05327511A publication Critical patent/JPH05327511A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To cancel the distortion of a pulse rising and falling, and to attain a D/A converter whose distortion can be reduced by smoothing a pulse signal equivalent to the positive number and negative number of a digital input signal, and operating an antiphase-addition. CONSTITUTION:A pulse width modulator 5 generates a pulse wave when the digital input signal is the positive number, and outputs a pulse wave 0 when the digital input signal is not the positive number. On the contrary, a pulse width modulator 6 outputs the pulse wave when the digital input signal is the negative number, and outputs the pulse wave 0 when the digital input signal is not the negative number. At that time, a constant phase relation between a pulse width center and a timing signal can be always attained, so that a waveform distortion due to a phase component can not be generated at the output waveform of the modulators 5 and 6. And also, a symmetrical relation between the pulse signal of a positive polarity and the pulse signal of a negative polarity can be attained by using a zero reference level as a center by the anti-phase-addition, so that a secondary harmonic wave distortion can not be generated. Therefore, the high frequency components of the outputs of the modulators 5 and 6 are removed by smoothing filters 7 and 8, and a smooth waveform is inputted to an antiphase-adder 9. Thus, the distortion of the rising and falling of the pulse wave can not be generated, and only a basic waveform can be outputted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はデジタル信号をアナログ
信号に変換するデジタル/アナログ変換(以下D/A変
換と称す)器に係り、特に、パルス幅変調(以下PWM
と称す)を用いたものに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog converter (hereinafter referred to as D / A converter) for converting a digital signal into an analog signal, and more particularly to pulse width modulation (hereinafter referred to as PWM).
Called)) is used.

【0002】[0002]

【従来の技術】D/A変換の一方法として、変換すべき
デジタル信号を、そのデータ値に応答するパルス幅を持
つパルス幅信号に変換した後、平滑用フィルタを通すこ
とによりアナログ信号に復調する方法が知られ、この方
法を用いると回路に高精度の部品を用いることなく高精
度のD/A変換を行うことが可能である。
2. Description of the Related Art As one method of D / A conversion, a digital signal to be converted is converted into a pulse width signal having a pulse width responsive to the data value thereof, and then passed through a smoothing filter to demodulate into an analog signal. There is known a method of doing so, and by using this method, highly accurate D / A conversion can be performed without using highly accurate parts in a circuit.

【0003】以下図面に基づき、従来のD/A変換器に
ついて説明する。図3は、従来のD/A変換器のブロッ
ク図である。この図において、1,2はパルス幅変調器
であり、それぞれタイミング信号に同期してデジタル入
力信号値に対応するパルス幅及びデジタル入力信号値の
補数値に対応するパルス幅を有するパルス幅信号を発生
する。3は逆相加算器であり、+端子に入力される波形
に対して−端子に入力される波形の位相を反転させて加
算し出力する。4は平滑用のフィルタである。
A conventional D / A converter will be described below with reference to the drawings. FIG. 3 is a block diagram of a conventional D / A converter. In the figure, reference numerals 1 and 2 denote pulse width modulators, which generate pulse width signals having a pulse width corresponding to a digital input signal value and a pulse width corresponding to a complement value of the digital input signal value, respectively, in synchronization with a timing signal. Occur. Reference numeral 3 denotes an anti-phase adder, which inverts the phase of the waveform input to the-terminal with respect to the waveform input to the + terminal, adds the waveform, and outputs the result. Reference numeral 4 is a smoothing filter.

【0004】次に図3の動作について説明するにあた
り、図4にデジタル入力信号値が、−5〜+5の11値
の場合の各部の波形を示す。パルス幅変調器1の出力A
は、デジタル入力信号値に対応するパルス幅を有するパ
ルス幅信号となる。パルス幅変調器2の出力Bは、デジ
タル入力信号値の補数値に対応するパルス幅を有するパ
ルス幅信号となる。パルス波AとBが逆相加算された出
力Cは、そのパルス幅の中心位置がタイミング信号と常
に一定の位相関係を有し、且つゼロ基準レベルを中心と
して正極性のパルス信号と負極性のパルス信号とが、対
称な関係になる。
Next, in explaining the operation of FIG. 3, waveforms of respective parts when the digital input signal value is 11 values of -5 to +5 are shown in FIG. Output A of pulse width modulator 1
Becomes a pulse width signal having a pulse width corresponding to the digital input signal value. The output B of the pulse width modulator 2 becomes a pulse width signal having a pulse width corresponding to the complement of the digital input signal value. The output C in which the pulse waves A and B are added in anti-phase has a center position of the pulse width thereof which has a constant phase relationship with the timing signal, and a positive pulse signal and a negative pulse centered on the zero reference level. It has a symmetrical relationship with the pulse signal.

【0005】パルス幅の中心位置がタイミング信号と常
に一定の位相関係にあることにより、位相成分に起因す
る波形歪みが生じなくなる。又、ゼロ基準レベルを中心
として正極性のパルス信号と負極性のパルス信号とが対
称な関係にあることにより、パルス信号の非対称性に起
因する2次高調波歪を抑圧している。その結果、平滑フ
ィルタ4の出力には、歪の無いアナログ信号が出力され
るというものである。
Since the center position of the pulse width always has a constant phase relationship with the timing signal, waveform distortion due to the phase component does not occur. Further, since the positive polarity pulse signal and the negative polarity pulse signal are symmetrical with respect to the zero reference level, the second harmonic distortion due to the asymmetry of the pulse signal is suppressed. As a result, an analog signal without distortion is output to the output of the smoothing filter 4.

【0006】[0006]

【発明が解決しようとする課題】しかしながら上記の様
な構成では、逆相加算器3として通常用いられるオペア
ンプのスルーレートが有限であるため、パルス波AとB
を逆相加算する際、パルスの立ち上がり時、立ち下がり
時に新たな歪を生じるという問題点があった。
However, in the above configuration, since the slew rate of the operational amplifier normally used as the anti-phase adder 3 is finite, the pulse waves A and B are
However, there is a problem that when the pulse is added in the opposite phase, a new distortion is generated at the rising and falling edges of the pulse.

【0007】本発明は上記の問題点を解決するもので、
位相成分による波形歪み及び2次高調波歪みを発生する
ことなく、また、パルスの立ち上がり時、立ち下がり時
にも歪を発生することがないD/A変換器を提供するも
のである。
The present invention solves the above problems.
The present invention provides a D / A converter that does not generate waveform distortion and second harmonic distortion due to a phase component, and does not generate distortion at the rising and falling edges of a pulse.

【0008】[0008]

【課題を解決するための手段】この目的を達成するため
に本発明によるD/A変換器は、タイミング信号に同期
して取り込まれるデジタル入力信号が正数のとき所定の
パルス幅を有するパルス幅信号に変換する第1のパルス
幅変調器と、前記デジタル入力信号が負数のとき所定の
パルス幅を有するパルス幅信号に変換する第2のパルス
幅変調器と、前記第1のパルス幅変調器の出力を平滑す
る第1のフィルタと、前記第2のパルス幅変調器の出力
を平滑する第2のフィルタと、前記第1、第2のフィル
タ出力の差分を取り出力する逆相加算器から構成されて
いる。
In order to achieve this object, a D / A converter according to the present invention has a pulse width having a predetermined pulse width when a digital input signal taken in in synchronization with a timing signal is a positive number. A first pulse width modulator for converting to a signal, a second pulse width modulator for converting to a pulse width signal having a predetermined pulse width when the digital input signal is a negative number, and the first pulse width modulator From the first filter that smoothes the output of the second pulse width modulator, the second filter that smoothes the output of the second pulse width modulator, and the anti-phase adder that outputs the difference between the outputs of the first and second filter It is configured.

【0009】[0009]

【作用】上記の構成によって、デジタル入力信号の正数
と負数に相当するパルス幅信号の各々を平滑した後に逆
相加算する様にしたため、パルスの立ち上がり、立ち下
がりにおける歪を打ち消すことができ、歪の少ないD/
A変換を行なうことができる。
With the above configuration, since the pulse width signals corresponding to the positive and negative numbers of the digital input signal are smoothed and the antiphase addition is performed, the distortion at the rising and falling edges of the pulse can be canceled. D / with little distortion
A conversion can be performed.

【0010】[0010]

【実施例】以下図面に基づき本発明の説明を行う。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

【0011】図1は本発明によるD/A変換器の実施例
である。図1において、5,6はパルス幅変調器であ
り、それぞれタイミング信号に同期して取り込まれるデ
ジタル入力信号を所定パルス幅を有するパルス幅信号に
変換する。7,8はパルス幅変調器の出力を平滑するフ
イルタである。9は、逆相加算器である。
FIG. 1 shows an embodiment of a D / A converter according to the present invention. In FIG. 1, reference numerals 5 and 6 are pulse width modulators, which convert a digital input signal that is taken in in synchronization with a timing signal into a pulse width signal having a predetermined pulse width. Reference numerals 7 and 8 are filters for smoothing the output of the pulse width modulator. 9 is an anti-phase adder.

【0012】以上の様に構成された本実施例のD/A変
換器について、以下その動作を説明する。図2はデジタ
ル入力信号値が−5〜+5の11値の場合のパルス幅変
調器の出力波形である。デジタル入力信号が与えられる
と、パルス幅変調器5,6は入力される値に応じたパル
ス幅のパルス波を発生する。パルス幅変調器5は、デジ
タル入力信号が正数(+1〜+5)のときのみパルス波
を発生し、それ以外(−5〜0)のときはパルス波0を
出力する。パルス幅変調器6は、デジタル入力信号が負
数(−5〜−1)のときのみ、パルス波を発生し、それ
以外(0〜+5)のときはパルス波0を出力する。ここ
でパルス幅変調器の出力波形は、パルス幅の中心位置が
タイミング信号と常に一定の位相関係にあることによ
り、位相成分に起因する波形歪みは生じない。又、逆相
加算することにより、ゼロ基準レベルを中心として正極
性のパルス信号と負極性のパルス信号とが対称な関係と
なるため、パルス信号の非対称性に起因する2次高調波
歪も発生しない。次にパルス幅変調器5,6の出力は、
それぞれ平滑用のフィルタ7,8により高周波成分が除
去されるため、逆相加算器9にはなめらかな波形が入力
される。このため、パルス波の立ち上がり、立ち下がり
に伴う歪は発生せず、基本波のみが出力される。
The operation of the D / A converter of the present embodiment constructed as above will be described below. FIG. 2 shows an output waveform of the pulse width modulator when the digital input signal value is 11 values from -5 to +5. When the digital input signal is given, the pulse width modulators 5 and 6 generate pulse waves having a pulse width according to the input value. The pulse width modulator 5 generates a pulse wave only when the digital input signal is a positive number (+1 to +5), and outputs a pulse wave 0 when the digital input signal is other than that (-5 to 0). The pulse width modulator 6 generates a pulse wave only when the digital input signal is a negative number (−5 to −1), and outputs a pulse wave 0 otherwise (0 to +5). Here, in the output waveform of the pulse width modulator, since the center position of the pulse width always has a constant phase relationship with the timing signal, the waveform distortion due to the phase component does not occur. In addition, since the positive-polarity pulse signal and the negative-polarity pulse signal have a symmetrical relationship with the zero reference level as the center by performing the anti-phase addition, the second harmonic distortion caused by the asymmetry of the pulse signal also occurs. do not do. Next, the outputs of the pulse width modulators 5 and 6 are
Since high frequency components are removed by the smoothing filters 7 and 8, respectively, a smooth waveform is input to the anti-phase adder 9. Therefore, distortion due to rising and falling of the pulse wave does not occur, and only the fundamental wave is output.

【0013】なお、本実施例においては、逆相加算器9
の出力に更に平滑用のフィルタを接続しても良いことは
いうまでもない。
In the present embodiment, the anti-phase adder 9
It goes without saying that a smoothing filter may be further connected to the output of the.

【0014】[0014]

【発明の効果】以上述べた様に本発明は、タイミング信
号に同期して取り込まれるデジタル入力信号が正数のと
き所定のパルス幅を有するパルス幅信号に変換する第1
のパルス幅変調器と、前記デジタル入力信号が負数のと
き所定のパルス幅を有するパルス幅信号に変換する第2
のパルス幅変調器と、前記第1のパルス幅変調器の出力
を平滑する第1のフィルタと、前記第2のパルス幅変調
器の出力を平滑する第2のフィルタと前記第1、第2の
フィルタ出力の差分を取り出力する逆相加算器の出力を
D/A変換器出力としたことにより、パルス波の立ち上
がり、立ち下がりに伴う歪を発生することなく、2次高
調波歪の発生を抑えることができるという優れた効果を
有するものである。
As described above, according to the present invention, when the digital input signal taken in in synchronization with the timing signal is a positive number, it is converted into a pulse width signal having a predetermined pulse width.
A pulse width modulator for converting the digital input signal into a pulse width signal having a predetermined pulse width when the digital input signal is a negative number;
Pulse width modulator, a first filter that smoothes the output of the first pulse width modulator, a second filter that smoothes the output of the second pulse width modulator, and the first and second filters. Since the output of the anti-phase adder that takes the difference of the filter output of and is output is the D / A converter output, the second harmonic distortion is generated without the distortion caused by the rise and fall of the pulse wave. It has an excellent effect that the above can be suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明によるD/A変換器の実施例を示すブロ
ック図
FIG. 1 is a block diagram showing an embodiment of a D / A converter according to the present invention.

【図2】図1におけるパルス幅変調器の出力波形2 is an output waveform of the pulse width modulator in FIG.

【図3】従来のD/A変換器を示すブロック図FIG. 3 is a block diagram showing a conventional D / A converter.

【図4】従来のD/A変換器における各部の出力波形FIG. 4 is an output waveform of each part in a conventional D / A converter.

【符号の説明】[Explanation of symbols]

1,2,5,6 パルス幅変調器 3,9 逆相加算器 4,7,8 平滑用フィルタ 1, 2, 5, 6 Pulse width modulator 3, 9 Anti-phase adder 4, 7, 8 Smoothing filter

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】タイミング信号に同期して取り込まれるデ
ジタル入力信号が正数のとき所定のパルス幅を有するパ
ルス幅信号に変換する第1のパルス幅変調器と、前記デ
ジタルに入力信号が負数のとき所定のパルス幅を有する
パルス幅信号に変換する第2のパルス幅変調器と、前記
第1のパルス幅変調器の出力を平滑する第1のフィルタ
と、前記第2のパルス幅変調器の出力を平滑する第2の
フィルタと、前記第1、第2のフィルタ出力の差分を取
り出力する逆相加算器を備えたことを特徴とするデジタ
ル/アナログ変換器。
1. A first pulse width modulator for converting a digital input signal, which is taken in synchronization with a timing signal, into a pulse width signal having a predetermined pulse width when the digital input signal is a positive number, and the digital input signal is a negative number. At this time, a second pulse width modulator for converting into a pulse width signal having a predetermined pulse width, a first filter for smoothing the output of the first pulse width modulator, and a second pulse width modulator A digital / analog converter comprising a second filter for smoothing an output and an anti-phase adder for taking a difference between outputs of the first and second filters and outputting the difference.
JP13330792A 1992-05-26 1992-05-26 Digital/analog converter Pending JPH05327511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13330792A JPH05327511A (en) 1992-05-26 1992-05-26 Digital/analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13330792A JPH05327511A (en) 1992-05-26 1992-05-26 Digital/analog converter

Publications (1)

Publication Number Publication Date
JPH05327511A true JPH05327511A (en) 1993-12-10

Family

ID=15101613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13330792A Pending JPH05327511A (en) 1992-05-26 1992-05-26 Digital/analog converter

Country Status (1)

Country Link
JP (1) JPH05327511A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7825840B2 (en) * 2005-01-26 2010-11-02 Robert Bosch Gmbh Delta sigma modulator
US11022676B2 (en) 2014-09-12 2021-06-01 Denso Corporation Filter apparatus and target detection apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7825840B2 (en) * 2005-01-26 2010-11-02 Robert Bosch Gmbh Delta sigma modulator
US11022676B2 (en) 2014-09-12 2021-06-01 Denso Corporation Filter apparatus and target detection apparatus

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