JPH05244008A - Digital-to-analog converter device - Google Patents

Abstract

PURPOSE:To increase the number of gradations of an input digital signal without increasing the clock frequency of a D/A converter system which employs pulse- width modulation. CONSTITUTION:Two pulse generators 1 and 2, a detecting means 3 which detect pulse widths that those pulse generators should generate reaching a specific value, and an adder 4 which adds the two pulse generator outputs are prepared. The leading edge of a pulse (pulse 1) generated by one pulse generator is timed to the trailing edge of a pulse (pulse 2) generated by the other pulse generator; and the pulse 1 is modulated on the basis of the leading edge and the pulse 2 is modulated on the basis of the trailing edge. When the pulse width of the generated pulse is equal to the period of the pulse or zero, the detecting means controls the pulse widths of the leading and trailing pulses and the positions where the pulses rise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter device for performing D / A conversion by modulating the width of a pulse generated corresponding to input digital data, and more particularly to Δ
It is used together with a Σ modulator to perform D / A conversion.

[0002]

2. Description of the Related Art With recent advances in digital signal processing technology, the importance of D / A conversion technology, which is an interface between digital signals and analog signals, is increasing. Especially, among them, recently, pulse width modulation (hereinafter referred to as PWM) is performed after bit compression is performed using a ΔΣ modulator having a sampling frequency of much higher than the required sampling frequency fs, for example, 64fs. A method of obtaining an analog signal by performing the operation is often used. A conventional D / A converter is shown in FIG. 8 and will be described (for example, Radio Technical Magazine, August 1991, pp148.
~ 152).

By generating two types of pulses having a constant sum of pulse widths and always having the same falling edges at the same time according to the input digital signal, the subtractor 100 takes the difference between these pulses. , The power center of each pulse always generates a pulse with a constant cycle, and high-performance D / A conversion is performed.

[0004]

However, in the above structure, when a pulse having a width of 6 clocks, which is a pulse period, or a pulse having a pulse width of 0 is generated,
The number of rising edges and falling edges in this section is different from that in the other sections because the pulse is connected to the pulse one cycle before or the pulse disappears in that cycle, which causes distortion. Therefore, the gradation of the pulse width is 1
There are problems that only 5 patterns of ~ 5 can be obtained, and if the gradation is further increased, the cycle must be lengthened or the clock frequency must be increased.

In view of the above problems, the present invention is capable of generating a pulse having a pulse width equal to the pulse period or a pulse having a pulse width of 0 to increase the gradation of an input digital signal. The present invention provides a D / A conversion device that enables the above.

[0006]

[Means for Solving the Problems] To achieve this object
In addition, the D / A converter according to the present invention has
Data D_nBased on the
Pulse width W_nFirst and second pulse generation for
Living device and adding means for adding the first and second pulses
And a pulse to be generated by the first and second pulse generators
And a detection means to detect that the pulse width of is a specific value
And a D / A for converting the output of the adding means into a D / A conversion output.
The digital data D is a conversion device._nBased on
The rising edge of the pulse generated by the first pulse generator is
The fall time is t1_UPn, T1_DNn, The second pal
When the pulse generated by the pulse generator rises and falls
T2_{U Pn}, T2_DNn, The digital data D_nBy
Pulse width W specified by_nIs m clock
Time D_n= M, the detection means is D_n= 0
Or N is a detecting means for detecting N, and
The pulse generated by the pulse generator is the rising edge of the first pulse.
Rising time t1_UPnAnd at the fall of the second pulse
Tick t2_DNn-1Are equal, and the digital data D_n-1，
D_n, D_{n + 1}When ≠ 0, N, it is based on the output of the detecting means.
The rising time t1 of the first pulse_UPnAnd the above
Falling time t2 of pulse 2_DNnIs always N black
The digital data D_n
= N and 0, based on the detection means, the first and
And the pulse width W of the second pulse_nIs one clock long
The rising time t of the first pulse
1_UPn, Falling time t2 of the second pulse_{D Nn-1}Is 1 black
Of the pulse generated by the second pulse generator
Pulse width W _n-1Is shortened by one clock, and the first
Pulse rising time t1_{UPn + 1}, The rise of the second pulse
Fall time t2_DNnIs delayed by one clock, the first pulse
Pulse width W of the pulse generated by the generator_{n + 1}1 clock
It is made shorter.

[0007]

As described above, when the pulse width is equal to the pulse period and when the pulse width is 0, the pulse for one clock is cut and taken in from the pulse before and after the pulse. Then, the falling edge is present, and the gradation of the input digital signal can be increased without causing distortion.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a D / A converter according to the present invention. To explain this figure, reference numerals 1 and 2 _denote pulse generators, which generate pulses P1 _n and P2 _n having a predetermined pulse width in accordance with input digital data D _n . Here, the data D _n has seven gradations of −3 to +3, and the pulse generators 1 and 2 generate pulses with a pulse width of 0 to 6 according to the data D _n . 4 is an adder,
Input pulses P1 _n and P2 _n are added. Next, book D
The operation of the A / A converter will be described with reference to FIGS.

FIG. 2 shows the case of input data D _n = -2 to +2. (1) is the clock signal, (2) is the output P1 _n of the pulse generator 1, (3) is the output P2 _n of the pulse generator 2, and (4) is the output of the D / A converter. It is the output P _n . The section τ1 shows the case where the data D _n = 1. The pulse generators 1 and 2 are left-justified with respect to a pulse having a pulse width of 4 clocks and the pulse generator 1 is left-aligned with the rising edge as a reference. 2 occurs right justified based on the falling edge. The adder 4 adds these pulses, and as shown in (4) of FIG. 2, pulse width 2, amplitude +2
Output as a pulse. The section τ2 shows the case where the data D _n = 2. The pulse generators 1 and 2 generate the pulses having the pulse width of 5 clocks by the pulse generator 1 left-justified and the pulse generator 2 right-justified. .. The adder 4 adds these pulses and outputs a pulse having a pulse width of 4 and an amplitude of +2, as shown in (4) of FIG. The interval τ3 shows the case where the data D _n = −1, and the pulse generators 1 and 2
The pulse generator 1 generates left-justified pulses and the pulse generator 2 right-justifies pulses having a pulse width of 2 clocks. The adder 4 adds these pulses and outputs a pulse having a pulse width of 2 and an amplitude of -2, as shown in (4) of FIG.

As described above, a digital signal is converted into an analog signal by generating a pulse whose power center always has a constant period on the + side and the-side according to the positive or negative of the input data D _n .

FIG. 3 shows pulses generated by the pulse generators 1 and 2 when the input data D _n is ± 3.
(1) is a clock signal, (2) and (5) are pulse generator 1 output P1
_n , (3) and (6) are pulse generator 2 output P2 _n , (4) and (6) are D
It is the output P _n of the adder 4 which becomes the output of the / A converter. Here, the data D _n is stored in the intervals τ1, τ2, τ3 of (2), (3), and (4).
When inputting = + 1, +3, -1, (5), (6),
Data D _n = -1, -3, + in sections τ1, τ2, τ3 of (7)
The case where 1 is input is shown.

When +3 is input as the input data D _{n in the} interval τ2, as shown in (2) and (3) of FIG. 3, the interval τ1
In the final 1 clock of, the output of the pulse generator 1 is set to "H" and the output of the pulse generator 2 is set to "L". After this, the outputs of the pulse generators 1 and 2 are set to "H" for 6 clocks in the interval τ2. Then, in the first one clock of the interval τ3, the output of the pulse generator 1 is set to “L” and the output of the pulse generator 2 is set to “H”. By adding these pulses by the adder 4, it is possible to generate a pulse having a pulse width 6 in which the power center always has a constant cycle as shown in (4) of FIG.

Considering the pulses generated by the pulse generators 1 and 2, there is always an edge for each pulse, and the pulse width adjacent to the pulse with the maximum width is {maximum width-2 clocks} or less. If so, adjacent pulses will not be connected to each other. Therefore, the distortion due to the change in the number of edges does not occur as in the conventional example. By the way, when the D / A converter is connected to the output of the ΔΣ modulator as shown in the related art, particularly when the ΔΣ modulator is of high order (third order, fourth order or more), the sum of consecutive values is calculated. The absolute value can always be less than or equal to {twice the maximum value of the ΔΣ modulator output −2}.

Next, the case where -3 is input as the input data D _n in the interval τ 2 is shown in (5), (6) and (7) of FIG. In this case as well, by performing the same operation as when the data D _n = + 3 is input, a negative pulse having a pulse width of 6 whose power center always has a constant cycle as shown in (7) of FIG. 3 is generated. Can occur.

Also in this case, the pulse generators 1, 2
The pulse that is generated always has an edge for each pulse, and if the pulse width of the pulse adjacent to the pulse of zero pulse width is 2 clocks or more, the pulse does not disappear between the adjacent sections. .. Therefore, the distortion due to the change in the number of edges does not occur as in the conventional example.

FIG. 4 shows the pulse generator 1 and the ± 3 detection means.
It is a block diagram which shows a specific Example. This figure smells
, 10, 11, 12, and 13 are latches, and input data
TA D _nWith a clock signal synchronized with the period T
Data. 14 is a detector for detecting ± 3
And "H" are output. Reference numeral 15 is a ROM, which is provided to the terminal A.
Output the value as shown in (Table 1) for the obtained address.
To do. 16 is a parallel / serial converter (hereinafter, P
/ S converter) and input to inputs P5 to P0.
The output signal is output from Q in the order of P5, P4, ..., P0.
Force In this figure, the latches 10 and 11, the ROM 1
5, OR gate 17, AND gate 19, P / S converter
The portion constituted by the data 16 corresponds to the pulse generator 1.
Hit, latch 10, 12, 13, detector 14, invar
The part constituted by the controller 18 corresponds to the detecting means 3.
It

[0017]

[Table 1]

Next, the operation of the pulse generator 1 shown in FIG. 4 will be described. When the input D _n is written in the latch 10, the detector 14 outputs “H” when the output of the latch 10 = ± 3.

<When Inputs D _n-1 , D _n , D _{n + 1} ≠ ± 3>
The output of the detector 14 is the output for the input D _{n + 1} , and the output of the latch 13 is the output of the detector 14 for the input D _n−1, so both are “L”. Therefore, since the OR gate 17 and the AND gate 19 directly input the Q0 and Q5 outputs of the ROM 15 to the P0 and P5 terminals of the P / S converter 16, the P / S converter 16 of FIG.
Output the pulse as shown in (2).

<In the case of input D _n = + 3 or -3> Assuming that the inputs D _n-1 , D _{n + 1} ≠ ± 3, when the input D _n is fetched by the latch 10, the detector 14 Output is "H"
Becomes As a result, the output of the OR gate 17 becomes "H", P0 of the P / S converter 16 is given "H", and the final value of the output Q of the P / S converter 16 becomes "H" (FIG. 3). (2), (5), last 1 clock of interval τ1).
Next, the input D _n is taken in by the latch 11, and the RAM 15
Will be the address of. At this time, since the inputs D _n-1 and D _{n + 1} ≠ ± 3, the outputs of the latch 13 and the detector 14 are both "L".
The output of the ROM 15 is given as it is to the input of the P / S converter 16, is parallel / serial converted, and is output from the terminal Q ((2) and (5) in FIG. 3, section τ2).
In the next cycle, the output of the detector 14 which has become “H” due to the input D _n is taken into the latch 13, so that the AND gate 19 becomes “L” by the inverter 18. Since this value is given to the input P5 of the P / S converter 16, the first output value of the P / S converter 16 becomes “L” ((2) and (5) in FIG. 3, the first 1 in the interval τ3. clock).

FIG. 5 is a block diagram showing a specific embodiment of the pulse generator 2. In this figure, those having the same functions as those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted. Reference numeral 20 denotes a ROM, which outputs a value as shown in (Table 2) for the address given to the terminal A. In this figure, a portion constituted by the latches 10, 11, the ROM 20, the OR gate 17, the AND gate 19, and the P / S converter 16 corresponds to the pulse generator 1, and the latch 1
A portion constituted by 0, 12, 13 and the detector 14 and the inverter 18 corresponds to the detecting means 3.

[0022]

[Table 2]

Next, the operation of the pulse generator 2 shown in FIG. 5 will be described. <When Inputs D _n-1 , D _n , D _{n + 1} ≠ ± 3> The output of the detector 14 is the output for the input D _{n + 1} , and the output of the latch 13 is the detector 14 for the input D _n-1 . Is output,
Both are "L". ROM 20 as in the case of FIG.
Q5 to Q0 output of P of P / S converter 16
Since it is input to terminals 0 and P5, the P / S converter 16 outputs a pulse as shown in (3) of FIG.

<In the case of input D _n = + 3 or -3> Assuming that the inputs D _n-1 , D _{n + 1} ≠ ± 3, when the input D _n is taken into the latch 10, the detector 14 Output is "H"
Becomes The output of the AND gate 19 becomes "L" by the inverter 18, "L" is given to P0 of the P / S converter 16, and the final value of the output Q of the P / S converter 16 becomes "L" (Fig. (3), (6) of 3, last 1 clock of interval τ1). Then, the input D _n is taken into the latch 11 and becomes the address of the RAM 15. At this time, since the inputs D _n-1 and D _{n + 1} ≠ ± 3, the latch 13 and the detector 1
The outputs of 4 are both "L", the output of the ROM 20 is given to the input of the P / S converter 16 as it is, and is parallel / serial converted and output from the terminal Q (see FIG. 3).
(3), (6), interval τ2). In the next cycle, the output of the detector 14 which has become “H” due to the input D _n is taken into the latch 13, so that the OR gate 17 becomes “H”. Since this value is given to the input P5 of the P / S converter 16,
The first output value of the P / S converter 16 becomes “H” ((3) and (6) in FIG. 3, the first one clock of the interval τ3).

FIG. 6 shows another embodiment of the D / A converter according to the present invention. In this embodiment, the pulse generator 32 generates a pulse having a phase opposite to that of the pulse P2 _n generated by the pulse generator 2, and the pulse generator 1 and the pulse generator 32 generate by using the subtractor 33. Find the difference between pulses D
A / A conversion output. FIG. 7 shows the output waveform of each part in this embodiment. The waveforms (2), (4), (5) and (7) are the same as the waveforms (2), (4), (5) and (7) in FIG. Waveform
(3) and (6) have opposite phases to the waveforms (3) and (6) in FIG. In this case, the rising times of both pulses generated by the pulse generators 1 and 32 are always the same, and when the inputs D _n-1 , D _n , D _{n + 1} ≠ ± 3, the pulses are generated in each section τ _m . The sum of the times when is "H" is constant for 6 clocks. With this configuration, the subtractor 33 can remove the in-phase noise, and the SN ratio can be improved.

The pulse generators 1 and 2 shown in FIGS.
Although the individual circuits are shown as shown in FIG.
It goes without saying that 0, 11, 12, 13 and the detector 14 may be shared. Also, input D to the D / A converter
_Although 7 gradations of -3 to +3 are set as _n , more may be used. The point is that the process for the pulse before and after the pulse for the maximum value and the minimum value may be performed as shown in FIG. 3 or 7. Further, in FIG. 6, the output of the pulse generator 2 in FIG. 1 is reversed in phase to take a difference from the pulse generator 1, but the output of the pulse generator 1 is reversed in phase and compared with the pulse generator 2. It goes without saying that the difference may be taken.

As described above, according to the present invention, the first and second pulse generators 1, which generate the pulse having the predetermined pulse width W _n with the N clock as the cycle, based on the input digital data D _n . 2, adding means 4 for adding the first and second pulses, and detecting means 3 for detecting that the pulse width of the pulse to be generated by the first and second pulse generators is a specific value. And a rise / fall time of a pulse generated by the first pulse generator based on the digital data D _n. T1 _UPn , t
1 _DNn, the rise of the second pulse of the pulse generator generates, falling time of t2 _UPn, t2 _DNn, the digital data D _n pulse width W of the pulse specified by _n
If D _n = m when is m clocks, the detecting means is a detecting means for detecting D _n = 0 or N, and the pulses generated by the first and second pulse generators are: When the rising time t1 _UPn of the first pulse and the falling time t2 _{DNn-1 of} the second pulse are equal and the digital data D _n-1 , D _n , D _{n + 1} ≠ 0, N, Based on the output of the detection means, the rising time t1 _UPn of the first pulse and the falling time t1 of the second pulse.
The interval of 2 _DNn is controlled to always be N clocks, and when the digital data D _n = N and 0, the pulse width W _{n of} the first and second pulses is 1 based on the detecting means. As the clock becomes longer, the rising time t1 _UPn of the first pulse and the falling time t2 _DNn-1 of the second pulse are _advanced by one clock, and the pulse width W _n- of the pulse generated by the second pulse generator. ₁ becomes shorter by 1 clock, and the rising time t1 _{UPn + 1 of} the first pulse,
The falling time t2 _DNn of the second pulse is delayed by one clock, and the pulse width W _{n + 1} of the pulse generated by the first pulse generator is shortened by one clock.

[0028]

As is apparent from the above description, according to the present invention, each pulse always has a rising edge and a falling edge, and the level of a digital signal input without causing distortion is high. It has an excellent effect that the tone can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a D / A conversion device according to the present invention.

FIG. 2 is a waveform diagram showing pulses generated by pulse generators 1 and 2 when input ≠ 0 and 6 and output waveforms of a D / A converter in the same embodiment.

FIG. 3 is a waveform diagram showing the pulses generated by the pulse generators 1 and 2 at the time of input = 0 and 6 and the output waveform of the D / A converter in the embodiment.

FIG. 4 is a block diagram showing a specific embodiment of the pulse generator 1 and the ± 3 detection means 3 in the same embodiment.

FIG. 5 is a block diagram showing a concrete example of a pulse generator 2 and ± 3 detection means 3 in the same example.

FIG. 6 is a block diagram showing another embodiment of the D / A conversion device according to the present invention.

FIG. 7 is a waveform diagram showing pulses generated by the pulse generators 1 and 32 in FIG. 6 and output waveforms of the D / A conversion device.

FIG. 8 is a block diagram showing a configuration of a conventional D / A conversion device.

[Explanation of symbols]

 1,2,32 Pulse generator 3 ± 3 Detection means 4 Adder 15,20 ROM 16 P / S converter 33 Subtractor

Claims (2)

[Claims] 1. A first pulse generator and a second pulse generator that generate a pulse having a predetermined pulse width W _n with N clocks as a cycle based on input digital data D _n , and the first and second pulse generators.
An addition means for adding the second pulse and a detection means for detecting that the pulse width of the pulse to be generated by the first and second pulse generators has a specific value are provided, and the output of the addition means is provided. A D / A converter for outputting D / A conversion, wherein the rising and falling times of the pulse generated by the first pulse generator are t1 _UPn , t1 _DNn , and the second based on the digital data D _n . The rising and falling times of the pulse generated by the pulse generator are t2 _UPn , t
2 _DNn, when the pulse width W _n of pulses specified by the digital data D _n is assumed to be D _n = m When a m clocks, the detection means the detection means detects the D _n = 0 or N The first and second pulse generators generate a pulse having the same rising time t1 _UPn of the first pulse and falling time t2 _{DNn-1 of} the second pulse, and the digital data D _{n −1} , D _n , D _{n + 1} ≠ 0, N, the interval between the rising time t1 _UPn of the first pulse and the falling time t2 _DNn of the second pulse is based on the output of the detecting means. It is controlled so that it is always N clocks, and when the digital data D _n = N and 0, the pulse width W _{n of} the first and second pulses is lengthened by one clock based on the detection means. , The rise of the first pulse Galli time t1 _UPn, fall time t2 _DNn-1 of the second pulse becomes faster one clock, the pulse width W _n-1 pulses second pulse generator generates one clock shorter, also, the Rising time t of pulse 1
1 _{UPn + 1} , the fall time t2 _DNn of the second pulse is delayed by one clock, and the pulse width W _{n + 1} of the pulse generated by the first pulse generator is shortened by one clock. The D / A converter. 2. The pulse generator according to claim 1, wherein one of the pulses generated by the first and second pulse generators is generated in a reverse phase, and a subtraction unit is provided as an addition unit. D / A converter.