JP3369383B2 - Modulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulator used for radio equipment such as digital mobile communication.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram showing the structure of a conventional modulator. In FIG. 11, reference numerals 1 and 2 denote digital band limiting filters for band limiting the baseband I and Q signals 13 and 14, respectively. 3 and 4 are digital multipliers for multiplying the baseband I and Q signals by the carrier signal, and 5 is an S
A counter for calling the IN waveform signal and the COS waveform signal,
6 is a ROM for outputting a COS waveform signal, 7 is a ROM for outputting a SIN waveform signal, 8 is an adder for adding baseband I and Q signals, and 9 is a D / A conversion for converting a digital modulation signal into an analog modulation signal. The digital multipliers 3, 4 and the D / A converter 9 constitute a digitized quadrature modulator.

Reference numeral 10 is a low-pass filter that removes unnecessary frequency components of the analog modulation signal, 11 is an analog mixer that mixes the analog signal output by the low-pass filter 10 with the local oscillation signal 26 and up-converts, and 12 is output by the analog mixer 11. It is a band-pass filter that removes unnecessary frequency components of the analog signal thus generated.

In the modulator constructed as described above, first, the baseband I signal 13 and the baseband Q signal 14 are input to the digital band limiting filters 1 and 2, respectively,
Bandwidth limited. Next, the band-limited baseband I
The signal 15 and the baseband Q signal 16 are input to the digital multipliers 3 and 4, respectively. The sampling frequency clock 17 is input to the counter 5 and the D / A converter 9, respectively, and the counter 5 outputs a control signal 18. This control signal 18 is generated by the COS waveform generation ROM 6 and the SIN waveform generation R
Input to OM7, COS waveform signal 19, SIN respectively
The waveform signal 20 is output and input to the digital multipliers 3 and 4. Band-limited baseband I signal 15 and COS
The waveform signal 19 is multiplied by the digital multiplier 3 to obtain I
The signal 21 is output. The band-limited baseband Q signal 16 and the SIN waveform signal 20 are multiplied by the digital multiplier 4 and a Q signal 22 is output.

Next, the I signal 21 and the Q signal 22 are added by the adder 8 and the digital modulation signal 23 is output. Next, the digital modulation signal 23 is input to the D / A converter 9, and the analog quadrature modulation signal 24 is obtained. The analog quadrature modulation signal 24 has the unnecessary frequency component removed by the low-pass filter 10, and the analog quadrature modulation signal 25 is obtained. This analog quadrature modulation signal 25 is output to the analog mixer 11
To the local oscillation signal 26 and up-converted to obtain an analog signal 27. Finally, the analog signal 27 is input to the bandpass filter 12 and unnecessary frequency components are removed, whereby a modulated signal 28 is obtained.

[0006]

The modulated signal output from the above-mentioned modulator is generally up-converted by the analog mixer 11 by mixing the analog quadrature modulated signal 25 with the local oscillation signal 26 in the latter stage, The band pass filter 12 removes components other than the necessary signal components. However, as the frequency of the analog quadrature modulation signal 24 decreases, the steep bandpass filter 12 is required, and it becomes difficult to realize the bandpass filter 12. Therefore, it is necessary to increase the frequency of the modulation signal 28 output from the modulator. There is.

However, since the frequency of the analog quadrature modulation signal 24 output by the digitized quadrature modulator is determined by the operation speed of the digital multipliers 3 and 4, the quadrature modulation frequency in the digitized quadrature modulator having the above configuration is The limit is 1/4 of the processing speed of the digital multipliers 3 and 4. For example, if the number of operation bits is 10 bits, the current commercial
Since the processing speed of the 10-bit digital multiplier is limited to about 40 MHz, there is a drawback that the quadrature modulation signal frequency is limited to about 10 MHz.

The present invention solves the above-mentioned conventional drawbacks, and an object of the present invention is to provide a modulator capable of outputting a quadrature modulated signal having a frequency half the processing speed of a D / A converter. It is what

[0009]

In order to achieve the above object, the present invention comprises a digitized quadrature modulator including a parallel / serial converter, a polarity inverter, a delay circuit, a D / A converter and an analog adder. , A digitalized quadrature modulator without using a conventional digital multiplier.

According to the present invention, it is possible to output a quadrature modulation signal having a frequency which is 1/2 the processing speed of the D / A converter.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The embodiment of the present invention does not use a digital multiplier, but uses a parallel / serial converter, a polarity inverter, a delay circuit, a D / A converter, and an analog adder to digitize a quadrature modulator. Is configured. Hereinafter, each embodiment will be described with reference to FIGS. 1 to 10.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a modulation apparatus according to Embodiment 1 of the present invention.
In FIG. 1, reference numerals 1 and 2 denote baseband I and Q signals 13 and 14, respectively.
A digital band-limiting filter that limits each of the
31 and 32 are parallel / serial converters (hereinafter, P / S) that combine the signals of the two systems in time sequence into one signal.
S and S converters), 29 and 30 are polarity inverters that invert the polarity of the input signal, 33 is a delay circuit that delays the input signal by the sampling period / 2, and 34 and 35 are analog modulation signals of the digital modulation signal. A D / A converter 36 for converting into a signal is an analog adder, and the delay circuits 29, 30 or the analog adder 36 constitute a digitized quadrature modulator. Ten
Is a low-pass filter that removes unnecessary frequency components of the analog modulation signal, 11 is an analog mixer that mixes and up-converts the analog signal output by the low-pass filter 10 with the local oscillation signal 26, and 12 is a signal output by the analog mixer 11. It is a bandpass filter that removes unnecessary frequency components.

FIG. 9 is a timing chart of the digitized quadrature modulator shown in FIG. 1 and FIGS. A is a sampling clock and corresponds to 17 in FIG. B is a baseband I signal and corresponds to 15 in FIG.
C is a baseband Q signal and corresponds to 16 in FIG. D is a signal obtained by inverting the polarity of the baseband I signal and corresponds to 37 in FIG. E is a signal obtained by reversing the polarity of the baseband Q signal and corresponds to 38 in FIG. F is the baseband I signal 15 and D of B
The signal obtained by inverting the polarity of the baseband I signal 37 of 1 is combined in time order to form one system, which corresponds to 39 in FIG. G
Is C baseband Q signal 16 and E baseband Q signal
The signal obtained by inverting the polarity of 38 and synthesizing the signals in order of time and forming one system corresponds to 40 in FIG. H is a signal obtained by delaying the signal G by the sampling period / 2 and corresponds to 41 in FIG.
I is a signal obtained by converting the signal F (39) into an analog signal.
Corresponds to 42. J is a signal obtained by converting the signal H (41) into an analog signal and corresponds to 43 in FIG. K is a quadrature modulation signal.
Corresponding to 24 of.

In the modulator constructed as described above, first, the baseband I signal 13 and the baseband Q signal 14 are input to the digital band limiting filters 1 and 2, respectively,
Bandwidth limited.

Next, the band-limited baseband I signal
The signal 37 whose polarity is inverted by the polarity inverter 29 is obtained at 15. The baseband I signal 15 and the signal 37 are combined in time order by the P / S converter 31 into a single system signal, and a signal Il (nT) 39 is obtained. This signal Il (n
T) is represented by (Equation 1).

[0016]

[Equation 1]

However, I (nT); baseband I signal k; 0, 1, 2, ... T; sampling period as well, the bandlimited baseband Q signal 16 has its polarity inverted by the polarity inverter 30. A signal 38 is obtained. The baseband Q signal 16 and the signal 38 are combined in time order by the P / S converter 32 into a single system signal, and the signal 40
Is obtained. Next, the signal 40 is delayed by the sampling circuit / 2 by the delay circuit 33, and the signal Ql (nT) indicated by 41 is obtained. This signal Ql (nT) is expressed by (Equation 2).

[0018]

[Equation 2]

However, Q (nT); baseband Q signal k; 0, 1, 2 ... T; sampling period Next, signal 39 and signal 41 are D / A converters 34 and 35, respectively.
Is input to and converted into analog I and Q signals 42 and 43.
The analog I, Q signals 42, 43 are added by the analog adder 36, and the analog quadrature modulated signal S (nT /
2) is obtained. This analog quadrature modulation signal S (nT / 2)
Is expressed by (Equation 3).

[0020]

[Equation 3]

The analog quadrature modulation signal 24 has its unnecessary frequency components removed by the low-pass filter 10 to obtain the analog quadrature modulation signal 25. This analog quadrature modulation signal SS (t) is represented by (Equation 4).

[0022]

## EQU00004 ## SS (t) = I (t) COS {2.pi. (1 / 2T) t} + Q
(t) SIN {2π (1 / 2T) t} This analog quadrature modulation signal 25 is input to the analog mixer 11, mixed with the local oscillation signal 26 and up-converted to obtain the analog signal 27. Finally, the analog signal 27 is input to the bandpass filter 12 and the unnecessary frequency component is removed, whereby the modulated signal 28 is obtained.

As described above, a digital band limiting filter for band limiting the baseband I and Q signals, a parallel / serial converter, a polarity inverter, a delay circuit and a D / D converter.
A digitalized quadrature modulator including an A converter and an analog adder, a low-pass filter for removing unnecessary frequency components of the quadrature-modulated signal from the digitized quadrature modulator, and an analog signal output by the low-pass filter A modulator is composed of an analog mixer that mixes with a local oscillation signal and up-converts it, and a bandpass filter that removes unnecessary frequency components of the analog signal output by the analog mixer, and has a processing speed of 1 of the D / A converter. A quadrature modulation signal with a frequency of / 2 can be output.

As an example, when the number of operation bits is 10 bits, the operation speed of the current commercial digital multiplier is 40 MHz.
The processing speed of a commercially available D / A converter is about 400 MHz. Therefore, in the conventional configuration, the quadrature modulation frequency is 10
Although the limit is about MHz, in the first embodiment, the quadrature modulation frequency can be set to about 200 MHz.
It is possible to obtain a quadrature-modulated signal having a frequency of about double.

(Embodiment 2) FIG. 2 is a block diagram showing the configuration of a modulation apparatus according to Embodiment 2 of the present invention.
The difference between the second embodiment and the first embodiment is that an analog band limiting filter 44 for band limiting the analog signal 27 is provided in the rear stage, and the base band I in the front stage,
In the configuration, the digital band limiting filters 1 and 2 for the Q signals 13 and 14 are removed. Other blocks with the same functions as in Figure 1,
Signals and the like are denoted by the same reference numerals and detailed description thereof will be omitted.

Next, the operation of the second embodiment will be described with reference to FIG. 2, which is the same as that of the first embodiment until the analog signal 27 is obtained. The analog signal 27 is band-limited by the analog band-limiting filter 44, and the modulated signal 28 is obtained.

As described above, in the second embodiment, the number of operation bits is reduced by performing the band limitation by using the band limiting filter in the subsequent stage, and the speed of the digital quadrature modulator and the quadrature modulation signal are further reduced. The frequency can be increased.

(Third Embodiment) FIG. 3 is a block diagram showing the configuration of a modulation apparatus according to the third embodiment of the present invention.
The third embodiment differs from the first embodiment (FIG. 1) in that a high-order harmonic component of the analog quadrature modulation signal 24 is extracted as a desired signal and a bandpass filter 45 for removing unnecessary frequency components is provided. It is in. Other than that, the same reference numerals are given to the blocks and signals having the same functions as those in FIG.
Detailed explanation is omitted.

Next, the operation of the third embodiment will be described with reference to FIG. 3, which is the same as the first embodiment until the analog quadrature modulated signal 24 is obtained. Analog quadrature modulation signal 24
The bandpass filter 45 extracts a high-order harmonic component as a desired signal, removes unnecessary frequency components, and obtains an analog quadrature modulation signal 25. The analog quadrature modulation signal 25 is input to the analog mixer 11, mixed with the local oscillation signal 26 and up-converted to obtain the analog signal.
You get 27. The analog signal 27 is input to the bandpass filter 12 and unnecessary frequency components are removed, whereby a modulated signal 28 is obtained.

As described above, the third embodiment can further increase the frequency of the quadrature modulation signal by using the high-order harmonic component of the analog quadrature modulation signal as the desired signal.

(Embodiment 4) FIG. 4 is a block diagram showing the structure of a modulation apparatus according to Embodiment 4 of the present invention.
The difference between the fourth embodiment and the first embodiment (FIG. 1) is that the aliasing noise component of the analog quadrature modulation signal 24 is taken out as a desired signal and the unnecessary frequency component is removed. The configuration is provided with polarity reversing units 46 and 47 that perform polarity reversing. Other than that, the same reference numerals are given to the blocks and signals having the same functions as those in FIG.
Detailed explanation is omitted.

Next, the operation of the fourth embodiment will be described with reference to FIG. 4. The signals from the parallel / serial converters 31 and 32 will be described.
The process is the same as that of the first embodiment (FIG. 1) until 39 and 41 are obtained. The polarities of the signals 39 and 41 are inverted by the polarity inverters 46 and 47, respectively, and the signals 49 and 50 are obtained. Next, the signals 49 and 50 are input to the D / A converters 34 and 35, respectively, and converted into analog I and Q signals 42 and 43. The analog signals 42 and 43 are added by the analog adder 36 to obtain the analog quadrature modulation signal 24.

The bandpass filter 48 extracts the aliasing noise component of the analog quadrature modulation signal 24 as a desired signal, removes unnecessary frequency components, and obtains an analog quadrature modulation signal 25. Here, the aliasing noise component is a signal obtained by inverting the polarity of the fundamental wave component, so that the quadrature modulation signal can be extracted by extracting the aliasing noise component.

The analog quadrature modulation signal 25 is input to the analog mixer 11, mixed with the local oscillation signal 26 and up-converted to obtain an analog signal 27. Finally, the analog signal 27 is input to the bandpass filter 12 and unnecessary frequency components are removed, whereby a modulated signal 28 is obtained.

As described above, the fourth embodiment can further increase the frequency of the quadrature modulated signal by using the aliasing noise component of the analog quadrature modulated signal as the desired signal.

(Embodiment 5) FIG. 5 is a block diagram showing the configuration of a modulation apparatus according to Embodiment 5 of the present invention.
The fifth embodiment differs from the first embodiment (FIG. 1) in that the analog mixer 11 is replaced by an image removing mixer 51 capable of attenuating an image wave generated after up-conversion. Other than the above, blocks and signals having the same functions as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

Next, the operation of the fifth embodiment will be described with reference to FIG. 5, which is the same as the first embodiment until the analog quadrature modulated signal 25 is obtained. This analog quadrature modulated signal
25 is input to the image removal mixer 51, and the local oscillation signal
Analog signal 27 mixed and up-converted with 26
Is obtained.

The structure of the image removing mixer 51 shown in FIG. 5 will be described with reference to FIG. First, the local oscillation signal 26 is input to the 90-degree phase shifter 52 and the analog mixer 53, and the 90-degree phase shifter is input.
A signal 57 is obtained from 52. Next, the analog quadrature modulation signal
25 is input to the analog mixers 53 and 54, and the local oscillation signals 26 and 57 are mixed and up-converted to obtain signals 58 and 59, respectively. The signal 59 is then phase shifted 90 degrees by the -90 degree phase shifter 55 to obtain the signal 60. Finally, the signal 58 and the signal 60 are added by the analog adder 56 to obtain the analog signal 27.

By using the image removing mixer 51 as an up mixer, an image wave generated after up conversion can be attenuated. Since this image rejection mixer is the same as the analog quadrature modulator in principle, it can attenuate the image wave by about 30 dB.

Next, returning to FIG. 5, the analog signal 27 is input to the bandpass filter 12, and unnecessary frequency components are removed, whereby a modulated signal 28 is obtained.

As described above, in the fifth embodiment, by using the image removing mixer as the up mixer, the quadrature modulation frequency can be reduced as compared with the configuration of the first embodiment (FIG. 1), and the consumption can be further reduced. It is possible to reduce power consumption.

(Embodiment 6) FIG. 6 is a block diagram showing the configuration of a modulation apparatus according to Embodiment 6 of the present invention.
The sixth embodiment differs from the second embodiment (FIG. 2) in that the analog mixer 11 is replaced by an image removing mixer 51 capable of attenuating an image wave generated after up-conversion. Other blocks, signals, and the like having the same functions as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

Next, the operation of the sixth embodiment will be described with reference to FIG. 6, which is the same as the second embodiment until the analog quadrature modulated signal 25 is obtained. This analog quadrature modulated signal
25 is input to the image removal mixer 51, and the local oscillation signal
Analog signal 27 mixed and up-converted with 26
Is obtained. The image removing mixer 51 can be realized by the configuration shown in FIG. 10 as in the fifth embodiment. By using the image removal mixer 51 as an up mixer,
Image waves generated after up-conversion can be attenuated. In principle, this image rejection mixer is the same as the analog quadrature modulator, so the image wave is
The degree can be attenuated.

Next, the analog signal 27 is input to the analog band limiting filter 44 and band-limited to obtain the modulated signal 28.

As described above, in the sixth embodiment, by using the image removing mixer as the up mixer, the quadrature modulation frequency can be reduced more than that in the configuration of the second embodiment (FIG. 2) and the consumption can be further reduced. It is possible to reduce power consumption.

(Embodiment 7) FIG. 7 is a block diagram showing the configuration of a modulation apparatus according to Embodiment 7 of the present invention.
The seventh embodiment differs from the third embodiment (FIG. 3) in that the analog mixer 11 is replaced by an image removing mixer 51 capable of attenuating an image wave generated after up-conversion. Other than that, blocks and signals having the same functions as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Next, the operation of the seventh embodiment will be described with reference to FIG. 7. The operation is the same as that of the third embodiment until the analog quadrature modulated signal 25 is obtained. This analog quadrature modulated signal
25 is input to the image removal mixer 51, and the local oscillation signal
Analog signal 27 mixed and up-converted with 26
Is obtained. The image removing mixer 51 can be realized by the configuration shown in FIG. 10 as in the fifth embodiment. By using the image removal mixer 51 as an up mixer,
Image waves generated after up-conversion can be attenuated. In principle, this image rejection mixer is the same as the analog quadrature modulator, so the image wave is
The degree can be attenuated.

The analog signal 27 is input to the bandpass filter 12 and the unnecessary frequency components are removed,
A modulated signal 28 is obtained.

As described above, in the seventh embodiment, by using the image removing mixer as the up mixer, the quadrature modulation frequency can be reduced as compared with the configuration of the third embodiment (FIG. 3), and the consumption is further increased. It is possible to reduce power consumption.

(Embodiment 8) FIG. 8 is a block diagram showing the configuration of a modulation apparatus according to Embodiment 8 of the present invention.
The eighth embodiment differs from the fourth embodiment (FIG. 4) in that the analog mixer 11 is replaced by an image removing mixer 51 capable of attenuating an image wave generated after up-conversion. Other than that, blocks and signals having the same functions as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Next, the operation of the eighth embodiment will be described with reference to FIG. 8. The operation is the same as that of the fourth embodiment until the analog quadrature modulation signal 25 is obtained. This analog quadrature modulated signal
25 is input to the image removal mixer 51, and the local oscillation signal
Analog signal 27 mixed and up-converted with 26
Is obtained. The image removing mixer 51 can be realized by the configuration shown in FIG. 10 as in the fifth embodiment. By using the image removal mixer 51 as an up mixer,
Image waves generated after up-conversion can be attenuated. In principle, this image rejection mixer is the same as the analog quadrature modulator, so the image wave is
The degree can be attenuated.

The analog signal 27 is input to the bandpass filter 12 and the unnecessary frequency components are removed,
A modulated signal 28 is obtained.

As described above, in the eighth embodiment, by using the image removing mixer as the up mixer, the quadrature modulation frequency can be reduced as compared with the configuration of the fourth embodiment (FIG. 4), and the consumption can be further reduced. It is possible to reduce power consumption.

[0054]

As described above, according to the present invention, a digital / quadrature modulator is constituted by a parallel / serial converter, a polarity inverter, a delay circuit, a D / A converter, and an analog adder, and a digital multiplier is used. By constructing the digitized quadrature modulator without using it, it is possible to output a quadrature modulation signal having a frequency half the processing speed of the D / A converter.

When the number of operation bits is 10, the current commercial digital multiplier has an operational speed of about 40 MHz and the commercially available D / A converter has a processing speed of about 400 MHz. Therefore, orthogonal modulation frequency in the conventional configuration 1 0M Hz
In the present invention, the quadrature modulation frequency is
The frequency can be set to about 200 MHz, and a quadrature modulation signal having a frequency about 20 times that of the conventional configuration can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a modulation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a modulation device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a modulation device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a modulation device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a modulation device according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a modulation device according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a modulation device in a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a modulation device according to an eighth embodiment of the present invention.

FIG. 9 is a timing chart of the digitized quadrature modulator of FIGS. 1 to 8.

FIG. 10 is a configuration diagram of an image removal mixer that constitutes the modulation device according to the fifth to sixth embodiments of the present invention.

FIG. 11 is a block diagram showing a configuration of a conventional modulation device.

[Explanation of symbols]

1, 2 ... Digital band limiting filter, 10 ... Low pass filter, 11, 53, 54 ... Analog mixer, 12, 4
5, 48 ... band pass filter, 13 ... baseband I signal, 14 ... baseband Q signal, 15 ... bandlimited baseband I signal, 16 ... bandlimited baseband Q signal, 17 ... sampling frequency clock, twenty four…
Analog quadrature modulation signal, 25 ... Analog quadrature modulation signal 24
Analog quadrature modulation signal with unnecessary frequency components removed,
26 ... local oscillation signal, 27 ... analog quadrature modulation signal 24 up-converted analog signal, 28 ... modulation signal,
29, 30, 46, 47 ... Polarity inverter, 31, 32 ... Parallel / serial converter, 33 ... Delay circuit, 34, 35 ... D / A converter, 36, 56 ... Analog adder, 37 ... Baseband I
A signal whose polarity is inverted 38, a signal whose polarity is inverted from the baseband Q signal 39, A signal which is composed of 39 ...
Sampling period of 41 ... Signal 40
Signal delayed by 2 42 ... Analog I signal 43 ...
Analog Q signal, 44 ... Analog band limiting filter,
49 ... a signal whose signal 39 is inverted in polarity, 50 ... a signal whose signal is inverted in polarity, 51 ... an image rejection mixer, 52 ... a 90-degree phase shifter, 55 ...- 90-degree phase shifter, 57 ... a local oscillation signal 26
90-degree phase-shifted signal, 58 ... Signal 25 and signal 26 mixed signal, 59 ... Signal 25 and signal 57 mixed signal, 60 ... Signal 59 phase-shifted by -90 degree.

Continuation of the front page (56) Reference JP-A-7-273818 (JP, A) JP-A-6-97969 (JP, A) JP-A-7-143196 (JP, A) JP-A-4-290337 (JP , A) JP 6-252972 (JP, A) JP 6-69969 (JP, A) JP 3-179954 (JP, A) JP 6-133293 (JP, A) JP 6-104943 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27/20 H04L 27/00

Claims (5)

(57) [Claims] 1. A digital band limiting filter for band limiting baseband I and Q signals, a polarity inverter for inverting the polarity of an output signal from the digital band limiting filter, the digital band limiting filter and a polarity inverter. , A parallel / serial converter for synthesizing the signals in chronological order into one system signal, a delay circuit for delaying the output signal from the parallel / serial converter of the baseband Q signal by a sampling period / 2, and the delay circuit D / A converter for converting a digital signal of the baseband Q signal from the parallel / serial converter and an analog signal of the baseband I signal from the parallel / serial converter, and adding the analog-converted baseband I and Q signals for quadrature A digitized quadrature modulator including an analog adder for obtaining a modulated signal; A low-pass filter that removes unnecessary frequency components of the quadrature-modulated signal from the quadrature-modulated modulator, an analog mixer that mixes the analog signal output by the low-pass filter with a local oscillation signal and up-converts, and an analog mixer that outputs the analog signal output by the analog mixer. A bandpass filter for removing an unnecessary frequency component of an analog signal to obtain an analog modulated signal. 2. The modulator according to claim 1, wherein band limitation is performed on an analog signal from the analog mixer by using an analog band limiting filter in a stage subsequent to the analog mixer. 3. A digital band limiting filter for band limiting the baseband I and Q signals, a polarity inverter for inverting the polarity of the output signal from the digital band limiting filter, the digital band limiting filter and the polarity inverting device. , A parallel / serial converter for synthesizing the signals in chronological order into one system signal, a delay circuit for delaying the output signal from the parallel / serial converter of the baseband Q signal by a sampling period / 2, and the delay circuit D / A converter for converting a digital signal of the baseband Q signal from the parallel / serial converter and an analog signal of the baseband I signal from the parallel / serial converter, and adding the analog-converted baseband I and Q signals for quadrature A digitized quadrature modulator including an analog adder for obtaining a modulated signal; A high-order harmonic component is extracted as a desired signal from a quadrature modulation signal from a digital quadrature modulator, and a bandpass filter that removes unnecessary frequency components and an analog signal output by the bandpass filter are mixed with a local oscillation signal. A modulator comprising: an up-converting analog mixer; and a bandpass filter for removing unnecessary frequency components of an analog signal output by the analog mixer. 4. A digital band limiting filter for band limiting the baseband I and Q signals, a polarity inverter for inverting the polarity of an output signal from the digital band limiting filter, the digital band limiting filter and a polarity inverting device. , A parallel / serial converter for synthesizing the signals in chronological order into one system signal, a delay circuit for delaying the output signal from the parallel / serial converter of the baseband Q signal by a sampling period / 2, and the delay circuit A polarity inverter for inverting the polarity of the digital signal of the baseband Q signal from the parallel / serial converter and the polarity of the digital signal of the baseband I signal from the parallel / serial converter; An analog for obtaining a quadrature modulation signal by adding the analog-converted baseband I and Q signals A digitized quadrature modulator configured by an adder, a bandpass filter that removes unnecessary frequency components of the quadrature modulation signal from the digitized quadrature modulator, and an analog signal output by the bandpass filter is locally oscillated. A modulation device comprising: an analog mixer for mixing and up-converting a signal, and a bandpass filter for removing an unnecessary frequency component of the analog signal output by the analog mixer to obtain an analog modulated signal. 5. A method according to claim, characterized by using an image reject mixer as an up-conversion mixer 1
4. The modulation device according to any one of 4 above.