JPH11163953A - Digital quadrature modulator and demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent gain difference, phase difference and a DC offset from occurring between in-phase component data and orthogonal component data by providing one D/A converter and executing a digital signal processing in sampling frequency conversion and an orthogonal modulation. SOLUTION: Input data is converted into a sampling frequency by an interpolator 4, sent to a filter 6 and, moreover, transmitted to a multiplier 8. In the same way, orthogonal component data of the sampling frequency is inputted to the interpolator 5 with an input terminal 2 and orthogonal component data which is converted into the sampling frequency is transmitted to the multiplier 9 through the interpolator 5 and a filter 7. In-phase component data converted into the sampling frequency is multiplied by cos(2.π.fcT) by the multiplier 8 and orthogonal data is multiplied by sin(2.π.fc.T) by the multiplier 9. Then, they are added by an adder 10, transmitted to the D/A converter 11, converted into analog data and outputted as orthogonally converted data through an output terminal 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital quadrature modem used for communication equipment, transmission equipment, and the like.

[0002]

2. Description of the Related Art In the following description, fs 'and fs are sampling frequencies (fs' = fs / 4) and T = n / fs (n: integer).
fc is a carrier frequency, and fc = fs / 4.

FIG. 12 is a block diagram showing an example of a conventional quadrature modulator. 1 and 2 are input terminals, 3 is an output terminal, 4 and 5
Is an interpolator, 6 and 7 are digital filters of the operating frequency fs, 94 and 95 are D / A converters, 96 and 97 are analog multipliers,
98 is an analog adder, 128 is an oscillator of frequency fs', 129
Is a 90 degree phase shifter. Input terminal 1 is connected to interpolator 4,
The interpolator 4 is connected to a filter 6. The filter 6 has a D /
The D / A converter 94 is connected to a multiplier 96. The multiplier 96 is connected to an adder 98, and the adder 98 is connected to the output terminal 3. Similarly, input terminal 2 is connected to interpolator 5, which is connected to filter 7. The filter 7 is connected to a D / A converter 95, and the D / A converter 95
Is connected to the multiplier 97. The oscillator 128 is connected to the 90-degree phase shifter 129 and the multiplier 97, and the 90-degree phase shifter 129 is connected to the multiplier 96.

In FIG. 12, in-phase component data of a sampling frequency fs ′ is input to an interpolator 4 via an input terminal 1. The input data is frequency-converted to a sampling frequency fs by the interpolator 4 and sent to the filter 6. The filter 6 removes unnecessary frequency components from the transmitted data and sends the data to the D / A converter 94. The D / A converter 94
Converts the transmitted data into analog data and sends it to the analog multiplier 96. Similarly, orthogonal component data of the sampling frequency fs ′ is input to the interpolator 5 via the input terminal 2. The input data is frequency-converted to a sampling frequency fs by the interpolator 5 and sent to the filter 7. The filter 7 removes unnecessary frequency components from the transmitted data and sends the data to the D / A converter 95. The D / A converter
95 converts the sent data to analog data,
Send to analog multiplier 97. In the multiplier 97, the frequency fs
Is multiplied by the local oscillation signal generated from the oscillator 128, and sent to the adder 98. Similarly, in the multiplier 96, the oscillator 12
The local oscillation signal generated from 8 is converted to 9
The adder 98 is multiplied by an oscillation signal having a phase shifted by 0 degrees.
Send to The adder 98 adds the two input signals and outputs the result from the output terminal 3 as quadrature modulated data.

FIG. 15 is a block diagram showing an example of a conventional quadrature demodulator. 301 is an input terminal, 302 and 303 are output terminals, 304 is an A / D converter, 305 and 306 are multipliers, 307 and
308 is a digital filter. Input terminal 301 is A / D
The A / D converter 304 is connected to a multiplier 304 and a multiplier 305. The multiplier 305 is connected to a digital filter 307, and the digital filter 307 is connected to the output terminal 30.
Connect to 2. The multiplier 306 is connected to a digital filter 308, and the digital filter 308 is connected to the output terminal 30.
Connect to 3. In FIG. 15, a quadrature amplitude modulation signal having a carrier frequency fIF whose band is limited is input to multipliers 306 and 307 via an input terminal 301. The received signals input to the multipliers 306 and 307 are multiplied by the multipliers 306 and 307 by an oscillator 314 having a frequency fc (= fIF) and a quadrature local oscillation signal generated by a 90-degree phase shifter 313. The quadrature detection is performed on the in-phase component and the quadrature component. From the multiplier 306, quadrature detection is performed, and the in-phase component of the data is output and sent to the A / D converter 304. The A / D converter 304 converts the input in-phase component into a digital signal and sends it to a digital filter 308. The digital filter 308
Performs waveform shaping and frequency conversion (from sampling frequency fs to sampling frequency fs / 4) of the transmitted signal, and outputs
Output via 302. Then, the multiplier 307 outputs the orthogonal component of the orthogonally detected data and outputs the A / D signal.
Sent to converter 305. The A / D converter 305 converts the input quadrature component into a digital signal and sends it to a digital filter 309. The digital filter 309 performs waveform shaping and frequency conversion (from the sampling frequency fs to the sampling frequency fs / 4) of the transmitted signal, and outputs the signal via the output terminal 303.

FIG. 10 is a block diagram showing another example of a conventional quadrature modulator. This figure shows the oscillator of FIG.
Remove the 128 and 90 degree phase shifters 129 and replace with cos (2π fc
The t) signal and the sin (2 · π · fc · t) signal are input to a multiplier.

In FIG. 10, an input terminal 1 and an input terminal 2
12 until the in-phase component and the quadrature component data of the sampling frequency fs' from the input are sent to the analog multipliers 96 and 97, respectively. Here, the multiplier 96 on the in-phase component side multiplies cos (2 · π · fc · t) and sends the result to the adder 98. Similarly, the multiplier 97 on the orthogonal component side multiplies by sin (2 · π · fc · t) and sends the result to the adder 98. The adder 98 adds the transmitted data of the in-phase component and the data of the quadrature component, and outputs the result via the output terminal 3. still,
Here, t is a real number.

[0008]

In the above-mentioned prior art,
Because it is processed in analog, oscillator, 90 degree phase shifter,
A gain difference, a phase difference, and a DC offset are likely to occur between the in-phase component data and the quadrature component data due to the precision and aging of the multiplier, the adder, and the like, and it has been difficult to improve the stability and increase the precision. In addition, the performance was degraded due to an asymmetric modulation spectrum.

Next, in order to perform quadrature modulation and demodulation by digital processing, if the device is composed of a quadrature modulator, a quadrature demodulator, and a digital filter, a complicated signal generator, a multiplier, a high-speed digital filter LSI, etc. are required.
There is a problem that the circuit configuration becomes large-scale.

When the sampling frequency is quadrupled, the passband becomes narrower than the stopband, so that a steep filter must be designed, and it is difficult to design filter coefficients. For this reason, a method of performing twice the frequency conversion twice is often performed. However, since the sampling frequency conversion is performed twice, four filters for the in-phase component and the quadrature component are required, and the second sampling frequency is used. The conversion has a high operating frequency,
There is a disadvantage that a high-speed digital filter is required.

An object of the present invention is to eliminate the above disadvantages and achieve the following objects.

A first object of the present invention is to provide a digital quadrature modulator or quadrature demodulator in which a gain difference, a phase difference and a DC offset do not occur between in-phase component data and quadrature component data.

A second object of the present invention is to eliminate the use of a multiplier for the multiplication processing required at the time of quadrature modulation or quadrature demodulation and the synthesis of in-phase component data and quadrature component data, and to minimize the use of an adder. An object of the present invention is to provide a digital quadrature modulator that performs quadrature modulation processing.

[0014] A third object of the present invention is to perform four times sampling frequency conversion with two times sampling frequency conversion.
For a double sampling frequency conversion from half the sampling frequency to the sampling frequency, instead of a digital filter operating at the same frequency as the required sampling frequency,
It is an object of the present invention to provide a digital quadrature modulator constituted by using a digital filter whose operating frequency is 1/2 of the sampling frequency.

A fourth object of the present invention is to perform a quadrupling sampling frequency conversion by twice a double sampling frequency conversion.
2 from the frequency of 1/2 the sampling frequency to the sampling frequency fs
It is an object of the present invention to provide a digital quadrature modulator in which two digital filters for in-phase component data and quadrature component data required for double sampling frequency conversion are constituted by one digital filter.

A fifth object of the present invention is to provide a filter required for quadrupling the sampling frequency conversion and a digital quadrature modulator in which quadrature modulation processing is constituted by one digital filter.

[0017]

According to the present invention, in order to achieve the first object, the present invention is configured using digital signal processing.

To achieve the second object, the carrier frequency is 1/4 of the sampling frequency of the input data at the time of quadrature modulation or quadrature detection, and the modulation output or demodulation output is in-phase component data. Using the fact that the orthogonal component data is alternately multiplied by 1 or -1 and output, the process is simplified by replacing the necessary multiplier and adder with a selector and a sign inverter for the orthogonal modulation. Is formed by a digital circuit having a simple configuration without using a multiplier.

Further, in order to achieve the third object, the multiplier and adder required for the quadrature modulation are replaced with a selector and a sign inverter to perform processing, and the sampling frequency is reduced from 1/4 of the sampling frequency. Is performed by dividing the sampling frequency conversion into four times from 1/4 to 1/2 and from 1/2 to the sampling frequency twice. The interpolation process is performed by switching "0" and "data" at the operating frequency of the digital filter at the subsequent stage, and the sampling frequency from the latter half of the two times double sampling frequency conversion to the sampling frequency. In the conversion, the operating frequency of the digital filter is set to half the sampling frequency.

Further, in order to achieve the fourth object, a means for solving the second object of the present invention and a means for solving the third object are used, and two times of double sampling are performed. The double sampling frequency conversion in the latter stage of the frequency conversion is configured by using one digital filter for the in-phase component data and the quadrature component data.

In order to achieve the fifth object, a complex coefficient digital filter is used, and a filter necessary for quadrupling the sampling frequency conversion and a quadrature modulation processing function are formed by one digital filter. is there.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, fs' and fs
Is the sampling frequency (fs' = fs / 4), T = n / fs (n: integer), fc is the carrier frequency, and fc = fs / 4.

An embodiment which achieves the first object of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing an example of the quadrature modulator of the present invention. 1 and 2 are input terminals, 3 is an output terminal, 4 and 5 are interpolators, 6 and 7 are operating frequencies fs
, 8 and 9 are digital multipliers, 10 is a digital adder, and 11 is a D / A converter.

The input terminal 1 is connected to the interpolator 4,
Is connected to the filter 6. The filter 6 is connected to a multiplier 8, which is connected to an adder 10. Similarly, input terminal 2 is connected to interpolator 5, which is connected to filter 7. The filter 7 is connected to a multiplier 9, which is connected to the adder 10. The adder 10 is connected to a D / A converter 11, and the D / A converter 11 is connected to an output terminal 3.

In FIG. 1, in-phase component data of a sampling frequency fs ′ is input to an interpolator 4 via an input terminal 1. The input data is frequency-converted to a sampling frequency fs by the interpolator 4 and sent to the filter 6. The filter 6 removes unnecessary frequency components from the input data and sends the data to the multiplier 8. Similarly, orthogonal component data of the sampling frequency fs ′ is input to the interpolator 5 via the input terminal 2, passes through the interpolator 5 and the filter 7, and
The orthogonal component data that has been frequency-converted is sent to the multiplier 9. The in-phase component data that has been frequency-converted to the sampling frequency fs is multiplied by cos (2 · π · fc · T) by the multiplier 8,
Further, the orthogonal component data is sin (2 · π · f) by the multiplier 9.
c · T). The multiplied data of the multiplier 8 and the multiplier 9 are sent to an adder 10, respectively, added by the adder 10, and sent to a D / A converter 11. The D / A converter
11 converts the sent data to analog data,
The signal is output via the output terminal 3 as orthogonally modulated data.

FIG. 16 is a block diagram showing an example of the quadrature demodulator according to the present invention. The reference numerals used in the figure are the same as those in FIG. The input terminal 301 is connected to the A / D converter 315,
The A / D converter 315 is connected to multipliers 305 and 306. The multiplier 305 is connected to a digital filter 307, and the digital filter 307 is connected to an output terminal 302. The multiplier 30
6 is connected to a digital filter 308, which is connected to an output terminal 303.

In FIG. 16, via an input terminal 301,
Band-limited carrier frequency fIF (fIF = fs /
The quadrature amplitude modulation signal of 4) is input to the A / D converter 315.
The A / D converter 315 converts the input signal into digital data having a sampling frequency fs, and sends the digital data to multipliers 305 and 306. The multiplier 305 multiplies the received digital data by cos (2 · π · fs / 4 · T) as carrier data, performs quadrature detection, and sends the result to the filter 307. The filter 307 performs waveform shaping and frequency conversion (from the sampling frequency fs to the sampling frequency fs / 4) of the transmitted data. The frequency-converted data is output as an in-phase component data at an output terminal 302.
Is output via. Similarly, the multiplier 306 adds sin data, which is carrier data, to the transmitted digital data.
(2 · π · fs / 4 · T), and quadrature detection is performed.
Send to 8. The filter 308 performs waveform shaping and frequency conversion of the transmitted data (from the sampling frequency fs to the sampling frequency fs
/ 4). The frequency-converted data is output via the output terminal 303 as orthogonal component data.

As described above, by performing quadrature modulation and demodulation using digital signal processing, a digital quadrature modulator and a digital quadrature modulator that prevent a gain difference, a phase difference, and a DC offset from being generated between in-phase component data and quadrature component data. And a demodulator.

FIG. 11 shows that in-phase component data “A” is input to the input terminal 1 in FIG. 1 and cos (2 · π · fc · T) = cos (1 /
2 · π · fs · T) and the quadrature component data “B” are input to the input terminal 2 and sin (2 · π · fc · T) = sin (1/2 ·
π · fs · T) and data obtained by adding the data multiplied by (π · fs · T). As shown in FIG. 11, in-phase component data “A” and quadrature component data “B” are alternately selected at a frequency fs, and the selected data and the data whose sign is inverted are selected at a frequency fs / 2. It turns out that it is equal to the result of having alternately selected by.

Also, in FIG. 16, T = n / fs
(N: an integer), the carrier wave data is cos (2 · π · fs / 4 · T) = 1, 0, −1, 0,... Sin (2 · π · fs / 4 · T) = 0, 1, 0, -1,... Further, assuming that the transfer function H (Z) of the digital filters 307 and 308 for sampling frequency conversion is H (Z) = 1 + Z ^-1 + Z ^-2 + Z ^-3 , the input data of the digital filter has the in-phase component data side. 1 time of A / D converted data, 0, -1
Double and 0 are input in order, and 0, 1 time, 0, and -1 times of the A / D converted data are input in order on the orthogonal component data side. That is, the digital filter 307 on the in-phase component data side sets the coefficients of the digital filter to “1, 0, −1,
0 ”and the digital filter 308 on the orthogonal component data side.
If is set to "0, 1, 0, -1", orthogonal detection and sampling frequency conversion can be performed simultaneously.

An embodiment which achieves the second object of the present invention with the above-described configuration will be described with reference to FIGS. 2 and 17.
FIG. 2 is a block diagram showing an example of the quadrature modulator of the present invention. 1 and 2 are input terminals, 3 is an output terminal, 4 and 5 are interpolators, 6 and
7 is a digital filter having an operating frequency fs, 11 is a D / A converter, 12 is a selector for a switching frequency fs, 14 is a selector for a switching frequency fs / 4, and 13 is a sign inverter.

The input terminal 1 is connected to the interpolator 4
Is connected to the filter 6. The filter 6 is connected to a terminal of the selector 12. Similarly, input terminal 2 is connected to interpolator 5, which is connected to filter 7. The filter 7 is connected to a terminal of the selector 12. The terminal of the selector 12 is connected to the terminal of the selector 11 and the sign inverter 13.
The sign inverter 13 is connected to a terminal of the selector 11, and a terminal of the selector 11 is connected to the D / A converter 11. The D / A converter 11 is connected to the output terminal 3.

In FIG. 2, in-phase component data of a sampling frequency fs ′ is input to an interpolator 4 via an input terminal 1.
The interpolator 4 frequency-converts the input data to a sampling frequency fs and sends it to the filter 6. The filter 6 removes unnecessary frequency components from the transmitted data and sends the data to the terminal of the selector 12. Similarly, orthogonal component data of the sampling frequency fs' is input to the interpolator 5 through the input terminal 2, and
5 converts the input orthogonal component data into a sampling frequency fs and sends it to the filter 7. The filter 7 removes unnecessary components from the input data and sends the data to the terminal of the selector 12.

Next, as shown in FIG. 11, the in-phase component data and the quadrature component data frequency-converted to the sampling frequency are alternately switched at the frequency fs by the selector 12 and output. The selector 14 alternately outputs the switched data and the switched data at the frequency fs / 2 by the selector 14 and outputs the inverted data.
Send to D / A converter 11. The D / A converter 11 converts the transmitted data into analog data and outputs the data via the output terminal 3 as quadrature-modulated data. Therefore, digital modulation processing can be performed without using a multiplier and an adder.

FIG. 17 is a block diagram showing an example of the quadrature demodulator according to the present invention. 301 is an input terminal, 302 and 303 are output terminals, 310 and 311 are adders, 316, 317, and 318 are operating frequencies fs.
319 and 320 are shift registers of the operating frequency fs / 4. An input terminal 301 is connected to an A / D converter 315, which is an adder 310 and a shift register.
Connected to 316. The shift register 316 is connected to a shift register 317 and an adder 311, and the shift register 317
Is connected to the shift register 318 and the adder 310.
The shift register 318 is connected to the adder 311, and the adder 311 is connected to the shift register 320. The shift register 320 is connected to the output terminal 303. The adder 31
0 is connected to the shift register 319,
Is connected to the output terminal 302.

In FIG. 17, a quadrature amplitude modulation signal having a carrier frequency fIF (= fs / 4) whose band has been limited is input to an A / D converter 315 via an input terminal 301. The A / D converter 315 converts the input signal into digital data having a sampling frequency fs, and sends it to a shift register 316 and an adder 310. The shift register 316 operates at the frequency fs, and sends data delayed by one sample (= fs) to the shift register 317 and the adder 311. The shift register 317 also delays the data by one sample (= fs) and sends the data to the adder 310 and the shift register 318. The shift register
318 also delays the data by one sample (= fs) and sends it to adder 311. As described above, since the filter coefficient on the in-phase component side is “0, −1, 0, 1”, the output data from the A / D converter 315 is added from the data two samples before (the output of the shift register 317). Subtractor 310 subtracts. Similarly, the filter coefficient on the orthogonal component side is “−1, 0,
Since the value is 1,0 ", the data 3 samples before the output data of the A / D converter 315 (output of the shift register 316) is subtracted from the data 3 samples before (output of the shift register 318) by the addition 311. Since the sampling frequency is converted to the sampling frequency fs / 4, the adders 310 and 31
The output data of 1 is transferred to the shift register 319 of the operating frequency fs / 4.
And 320, respectively, and output from output terminals 302 and 303, respectively.

FIGS. 13 and 18 show another embodiment which achieves the second object of the present invention. FIG. 13 is a block diagram of the modulator, in which the configuration (digital interpolation filter) of the interpolator and the digital filter (operating frequency fs) in the configuration of FIG. 2 is configured by a shift register (operating frequency fs / 4). That is, the interpolator 4 and the digital filter 6 (operating frequency fs) are connected to the shift register 116 having the operating frequency fs / 4.
And an interpolator 5 and a digital filter 7 (operating frequency fs)
Is replaced by a shift register 117 having an operating frequency fs / 4.

The operation of FIG. 13 will be described below. here,
The quadruple frequency conversion processing by the interpolator is based on the sampling frequency fc (= fs / 4 (period: 41 / fs)) of the input data.
Cycle between “data” and “data”: 31 / fs is “0”
Is switched to be inserted instead of “data”. At this time, if the transfer function H (Z) of the digital filter having the operating frequency fs is given by the following equation, H (Z) = 1 + Z ^-1 + Z ^-2 + Z ^-3 , the output data of the digital filter is the input data before interpolation. It can be seen that the output data is equivalent to the output data held by the shift register at the operating frequency fs / 4. That is, it is possible to perform processing by replacing the digital interpolation filter with the operating frequency fs with a shift register with the operating frequency fs / 4.

FIG. 18 is a block diagram of the demodulator. In the configuration of FIG. 17, the operating frequency of the adder is not fs but fs.
4 shows a configuration in the case of operating at / 4. That is,
Data input to the adder 310 is received through the shift registers 321 and 323 of the operating frequency fs / 4, and data input to the adder 311 is received through the shift registers 322 and 324 of the operating frequency fs / 4. Alternatively, adders
Shift register 319 with operating frequency fs / 4 on the output side of 310
And the shift register 320 of the operating frequency fs / 4 on the output side of the adder 311 are deleted.

The operation of FIG. 18 will be described below. In FIG. 18, a quadrature amplitude modulation signal having a carrier frequency fIF (= fs / 4) whose band has been limited is input to an A / D converter 315 via an input terminal 301. The A / D converter 315 converts the input signal into digital data having a sampling frequency fs, and sends the digital data to a shift register 316 and a shift register 321. The shift register 316 is a shift register that operates at the frequency fs, and sends data delayed by one sample (= fs) to the shift register 317 and the shift register 322. The shift register
317 also delays the data by one sample (= fs) and sends it to shift register 323 and shift register 318. The shift register 318 also delays the data by one sample (= fs),
Send to shift register 324. The shift register 324 and the shift register 322 transfer the transmitted data,
The sampling frequency is converted and the operating frequency of the adder processing is set to fs / 4
And sends it to the adder 311. The shift register 321 and the shift register 323 each transmit the data,
The sampling frequency is converted and the operating frequency of the adder processing is set to fs / 4
And sends it to adder 310. As described above, the filter coefficient on the in-phase component side is “0, −1, 0, 1”.
The adder 310 subtracts the output data from the / D converter 315 (the output of the shift register 321) from the data (the output of the shift register 323) two samples before. Similarly, since the filter coefficient on the orthogonal component side is "-1, 0, 1, 0", the data one sample before the output data of the A / D converter 315 (the output of the shift register 322) is three samples. The previous data (the output of the shift register 324) is subtracted by an addition 311. The in-phase component output data (operating frequency fs / 4) of the adder 310 is output from the output terminal 302, and the adder 311
Output data (operating frequency fs / 4) is output terminal 3
Output from 03.

As shown in FIG. 18, the addition operation is performed at the frequency f
If the operation cannot be performed in S, the sampling frequency conversion is performed by the shift register of the operating frequency fS / 4 before the addition processing is performed, and then the addition processing is performed.
It only needs to operate at / 4.

FIGS. 14 and 19 are block diagrams showing another embodiment for achieving the second object of the present invention. FIG. 14 shows a modulator and FIG. 19 shows a demodulator. In FIG. 14, 116, 117, 11
8, 119 are shift registers having an operating frequency of fs / 4;
4, 125 are shift registers whose operating frequency is fs, and 120, 12
1, 122 and 123 are adders, and the other symbols are common to FIG. The input terminal 1 is connected to a shift register 116, which is connected to a shift register 118 and an adder 120. The shift register 118 is connected to the adder 120, and the adder 120 is connected to the adder 122. The adder 12
2 is connected to the terminal of the selector 12 and the shift register 124,
The shift register 124 is connected to the adder 122. The input terminal 2 is connected to a shift register 117, which is connected to a shift register 119 and an adder 121. The shift register 119 is connected to the adder 121, and the adder 121 is connected to the adder 123. The adder 123 is connected to the terminal of the selector 12 and the shift register 125,
The shift register 125 is connected to the adder 123. The terminal of the selector 12 is the same as the terminal of the selector 14
13 and the sign inverter 13 is connected to the terminal of the selector 14. The terminal of the selector 14 is a shift register
The shift register 111 is connected to the D / A converter 11, and the D / A converter 11 is connected to the output terminal 3.

The operation of FIG. 14 will be described below. FIG.
In the case where the stopband attenuation is further increased than in FIG. 13, the transfer function H (Z) of the digital filter having the operating frequency fs is expressed by the following equation: H (Z) = (1 + Z ^-1 + Z ^-2 + Z ^-3 ) ² = (1 + Z ^-1 + Z ^-2 + Z ^-3 ) · (1 -Z ^-4 ) / (1 -Z ^-1 ), and the portion of (1 + Z ^-1 + Z ^-2 + Z ^-3 ) is the operating frequency fs / 4. In the shift register, the (1-Z ^-4 ) part is a shift register and an adder having the same operating frequency fs / 4.
The portion of (1-Z ^-1 ) can be constituted by a shift register having an operating frequency fs and an adder. The shift register 111 of the operating frequency fs / 4 latches the data sent from the terminal of the selector 14, adjusts the data timing, and sends the data to the D / A converter 11.

FIG. 19 shows an example in which an accumulating circuit is provided between the adder of FIG. 17 and the shift register preceding the output terminal. 325 and 326 are adders, 327 and 328 are shift registers of the operating frequency fs, 329 is a clear signal generation circuit, and other symbols are the same as those in FIG. The connection from the input terminal 301 to the adder 310 and the adder 311 is exactly the same as in FIG. 17, the adder 310 is connected to the adder 325, and the adder 325 is connected to the shift register 327 and the shift register 319. I do. The shift register 319 is connected to the output terminal 302. The adder 311 is connected to an adder 326, and the adder 326 is connected to a shift register 328 and a shift register 320. The shift register 320 is connected to the output terminal 303. The clear signal generation circuit 329 is connected to the shift registers 327 and 328.
The shift register 327 connects to the shift register 325, and the shift register 328 connects to the shift register 326.

The operation of FIG. 19 will be described below. FIG.
In the case where the stop band attenuation is further increased than in FIG. 18, the transfer function H (Z) of the digital filter having the operating frequency fs is expressed by the following equation: H (Z) = (1 + Z ^-1 + Z ^-2 + Z ^-3 ) ² = (1 + Z ^-1 + Z ^-2 + Z ^-3 ) (1 + Z ^-1 + Z ^-2 + Z ^-3 ). At this time, (1 + Z ^-1 + Z ^-2 + Z ^-3 ) at the preceding stage composed of the input terminal 301 to the adders 310 and 311 is constituted by a digital filter which combines the above quadrature detection processing and sampling frequency conversion processing. And (1 + Z ^-1 +
Considering that Z ^-2 + Z ^-3 ) may be output for each frequency fs / 4, the result of the previous stage is accumulated by an accumulator using an adder and a shift register of the operating frequency fs and accumulated four times. If a clear signal generating circuit is used to clear the shift register of the operating frequency fs so that the shift register of the operating frequency fs / 4 later captures and outputs the data and clears the accumulated result after the capture, the multiplier is not used. The circuit scale can be reduced.

Next, an embodiment which has achieved the third object of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing an example of the quadrature modulator of the present invention. 1 and 2 are input terminals, 15 and
16 is an interpolator, 17 and 18 are digital filters having an operating frequency of fs / 2, 19 and 20 are interpolators, and 21 and 22 are operating frequencies of fs.
, 12 and 14 are selectors, 13 is a sign inverter, 11 is a D / A converter, and 3 is an output terminal.

The input terminal 1 is connected to the interpolator 15 and
5 is connected to the filter 17. The filter 17 is connected to an interpolator 19, which is connected to a filter 21. The filter 21 is connected to a terminal of the selector 12. Similarly, terminal 2
Is connected to an interpolator 16, which is connected to a filter 18. The filter 18 connects to an interpolator 20, which in turn connects to a filter 22. The filter 22 is connected to the terminal of the selector 12. The terminal of the selector 12 is connected to the terminal of the selector 14 and the sign inverter 13, and the output of the sign inverter 13 is connected to the terminal of the selector 14. The terminal of the selector 14 is connected to the D / A converter 11, and the D / A converter 11 is connected to the output terminal 3. Hereinafter, this operation will be described. In-phase component data of the sampling frequency fs' is input to the interpolator 15 via the input terminal 1. The interpolator 15 frequency-converts the input data to a sampling frequency 2fs ′ (= fs / 2),
Send to filter 17. The filter 17 removes unnecessary frequency components from the input data and sends the data to the interpolator 19. The interpolator
19 converts the input data into a sampling frequency fs and sends it to the filter 21. The filter 21 removes unnecessary frequency components from the input data and sends the data to the terminal of the selector 12. Similarly, the sampling frequency fs ′ is input via the input terminal 2.
Are input to the interpolator 16. The interpolator 16 converts the frequency of the input data into a sampling frequency 2fs' (= fs / 2) and sends the data to the filter 18. The filter 18 removes unnecessary frequency components from the input data and sends the data to the interpolator 20. The interpolator 20 converts the input data into a sampling frequency fs
, And sends it to the filter 22. The filter 22 removes unnecessary frequency components from the input data and sends the data to the terminal of the selector 12. The selector 12 switches the in-phase component data and the quadrature component data obtained by the sampling frequency conversion at the frequency fs. This data is sent to the terminal of the selector 14 and also sent to the sign inverter 13. The sign inverter 13 outputs the sign-inverted data to the selector 14.
To the terminal. The selector 14 switches the two transmitted data at the frequency fs / 2 and sends the data to the D / A converter 11. The D / A converter 11 converts the data into analog data and outputs the data through the output terminal 3 as quadrature-modulated data.

Here, the interpolator 19 and the interpolator 20 in FIG.
Can be constituted by a selector which alternately switches between "data" and "0" at a frequency fs. The digital filter 21 and the digital filter 22 are FIR digital filters using a delay shift register, a multiplier and an adder. Can be configured. One embodiment of this configuration will be described with reference to FIG.

FIG. 4 is a block diagram showing the interpolators 19 and 20 and the filter 2 shown in FIG.
This is an example of a block diagram in which FIR digital filters have been substituted for 1 and 22. 23 and 24 represent "data" and "0" at frequency f.
Selector that switches alternately with s, 25, 26, 27, 28, 29, 4
1,42,43,44,45 are delay shift registers, 30,31,3
2, 33, 34, 35, 46, 47, 48, 49, 50, 51 are multipliers, 3
6, 37, 38, 39, 40, 52, 53, 54, 55, 56 are adders, 99
And 100 are FIR digital filters, and the other is the same as FIG. Input terminal 1 is connected to interpolator 15
5 is connected to the filter 17. The filter 17 is a selector 23
And the other input terminal of the selector 23 is connected to ground (grounded). The output terminal of the selector 23 is connected to a delay register 25 and a multiplier 30, and the delay register 25 is connected to a delay register 26 and a multiplier 31.
Connected to. The delay register 26 is connected to a delay register 27 and a multiplier 32, and the delay register 27 is connected to a delay register 28.
And the multiplier 33. The delay register 28 is connected to a delay register 29 and a multiplier 34, and the delay register 29 is connected to a multiplier 35. The multiplier 30 and the multiplier 31 are connected to an adder 36, and the adder 36 and the multiplier 32 are connected to an adder 37. The adder 37 and the multiplier 33 are connected to an adder 38, and the adder 38 and the multiplier 34 are connected to an adder 39.
The adder 39 and the multiplier 35 are connected to an adder 40, and the adder 40 is connected to a terminal of the selector 12. Similarly, input terminal 2 connects to interpolator 16, which in turn connects to filter 18. The filter 18 is connected to the terminal of the selector 24,
The other terminal of the selector 24 is connected to ground (grounded). The terminal of the selector 24 is connected to a delay register 41 and a multiplier 46, and the delay register 41 is connected to a delay register 42 and a multiplier 47. The delay register 42
Is connected to a delay register 43 and a multiplier 48, and the delay register 43 is connected to a delay register 44 and a multiplier 49. The delay register 44 is connected to a delay register 45 and a multiplier 50, and the delay register 45 is connected to a multiplier 51. The multiplier 46
And the multiplier 47 are connected to an adder 52, and the adder 52 and the multiplier 48 are connected to an adder 53. The adder 53 and the multiplier 49 are connected to an adder 54, and the adder 54 and the multiplier 50 are connected to an adder 55. The adder 55 and the multiplier 51 are connected to an adder 56, and the adder 56 is connected to an input terminal of the selector 12. The terminal of the selector 12 is connected to the terminal of the selector 14 and the sign inverter 13, and the sign inverter 13 is connected to the terminal of the selector 14. The terminal of the selector 14 is connected to the D / A converter 11, and the D / D converter 11 is connected to the output terminal 3. Here, the configuration of the delay registers 25 to 29, the multipliers 30 to 35, and the adders 36 to 40 is an FIR filter 99, and the configuration of the delay registers 41 to 45, the multipliers 46 to 51, and the adders 52 to 56 is an FIR filter. It is 100. FIG.
Is obtained by removing multipliers 31, 33, 35, 46, 48, 50 and adders 36, 38, 40, 52, 53, 55 from the configuration of FIG.
Here, the configuration of the delay registers 25 to 29, the multipliers 30, 32, and 34 and the adders 37 and 39 is the FIR filter 101, and the configuration of the delay registers 41 to 45, the multipliers 47, 49, and 51, and the adders 54 and 56. Is the FIR filter 102. FIG. 6 shows a configuration in which the selector 23 and the selector 24 are removed from the configuration of FIG. 5, and the two delay registers 25 and 26 are made into one, and the delay register 57 is made into two delay registers 27 and 28. In register 58,
The two delay registers 42 and 43 are combined into one to provide a delay register 59
In this configuration, the two delay registers 44 and 45 are integrated into a delay register 60, and the delay register 41 is omitted. Here, the delay registers 57, 58 and the multipliers 30, 32,
The configuration of 34 and the adders 37 and 39 is an FIR filter 103.
Delay registers 59, 60, multipliers 47, 49, 51, and adders
The configuration of 54 and 56 is the FIR filter 102.

Next, an example of the operation of FIG. 4 will be described. In-phase component data of the sampling frequency fs ′ is input to the interpolator 15 via the input terminal 1. The interpolator 15 converts the input data to a sampling frequency of 2fs' (= fs / 2),
Send to filter 17. The filter 17 removes unnecessary frequency components from the input data and sends the data to the selector 23. The selector 23 performs 0 interpolation by alternately switching between “data” and “0” at the frequency fs, and performs multipliers 30, 31, 32, 33,
The multiplication coefficients a0, a1, a2, a3, a4, and a5 of 34 and 35 are input to the FIR digital filter 99. At this time, the selector 23
Is output alternately as "data" and "0", the output data of the delay shift registers 29, 28, 27, 26, and 25 are respectively x0, x1, x2, x3, and x4, and the selector 23 When the selector 23 is connected in the data direction, the output of the FIR filter 99 is (x1.a4 + x3.a2 + x5.a0), and the output data of the selector 23 is x5.
Is connected in the ground direction, the output of the FIR filter 99 is (x0.a5 + x2.a3 + x4.a1). Similarly, the orthogonal component data of the sampling frequency fs ′ is input to the interpolator 16 via the input terminal 2. The interpolator 16 converts the input data to a sampling frequency of 2fs' (= fs / 2) and sends it to the filter 18. The filter 18 removes unnecessary frequency components from the input data and sends the data to the selector 24. The selector 24 performs 0 interpolation by alternately switching “data” and “0” at the frequency fs, and b0, b1, b
Multipliers 46, 47, 4 composed of multiplication coefficients of 2, b3, b4, b5
Input to FIR filter 100 having 8,49,50,51.
When the output data of the delay shift registers 45, 44, 43, 42, and 41 is y0, y1, y2, y3, and y4, and the output data of the selector 24 is y5, the selector 24 is connected to a data input terminal. In this case, the output of the FIR filter 100 is (y1 · b4 + y3 · b2 + y5 · b0),
When the input side of is connected to the ground direction of the terminal,
The output of the FIR filter 100 is (y0 · b5 + y2 · b3 + y4 · b
1) When the selector 23 and the selector 24 are connected in the data direction, the outputs of the FIR filters 99 and 100 are connected to the output of the FIR digital filter 99 on the in-phase component data side, and the selector 23 and the selector 24 are connected. Are connected in the direction of ground, the selector 12 is switched so as to be connected to the output of the FIR digital filter 100 on the orthogonal component data side. Thereafter, the same operation as described with reference to FIG. 3 is performed, and thus the description is omitted. Here, the output of the selector 12 is (x1 · a4 + x3 · a2
+ X5 · a0) and (y0 · b5 + y2 · b3 + y4 · b1) are output alternately, so that the configuration of the digital filter shown in FIG. 5 can be used. If 0 interpolation is not performed by the selector 23 and the selector 24, x5 = x4, x3
= x2, x1 = x0, y5 = y4, y3 = y2, y1 = y0, so FIG.
The FIR digital filter has an operating frequency fs / 2
Can be operated.

Next, an embodiment achieving the fourth object of the present invention will be described with reference to FIG. 1 and 2 are input terminals, 15 and 16
Is an interpolator, 17 and 18 are digital filters, 14, 61, 71,
72, 73 are selectors, 62, 63, 64, 65 are delay registers, 6
6, 67 and 68 are multipliers, 69 and 70 are adders, 200 is a digital filter, 13 is a sign inverter, 11 is a D / A converter, and 3 is an output terminal. The input terminal 1 is connected to an interpolator 15, which is connected to a filter 17. The filter 17 is a selector
Connect to terminal 61. Similarly, input terminal 2 is connected to interpolator 16
, And the interpolator 16 is connected to a filter 18. The filter 18 is connected to a terminal of the selector 61. The terminal of the selector 61 is connected to a delay register 62 and a multiplier 66,
The delay register 62 is connected to the delay register 63. The delay register 63 is connected to a delay register 64 and a multiplier 67, and the delay register 64 is connected to a delay register 65. Selector 71
Switches between the multiplication coefficient a0 and the multiplication coefficient b1,
Multiply by. Similarly, the selector 72 switches between the multiplication coefficient a2 and the multiplication coefficient b3 for the multiplier 67, and the selector 73 switches between the multiplication coefficient a4 and the multiplication coefficient b5 to multiply the multiplier 68. The multiplier 66 and the multiplier 67 are connected to an adder 69, and the adder 69 and the multiplier 68 are connected to an adder 70.
The adder 70 is connected to the terminal of the selector 14 and the sign inverter 13, and the sign inverter is connected to the terminal of the selector 14. The terminal of the selector 14 is connected to the D / A converter 11, and the D / A converter 11 is connected to the output terminal 3. Here, the configuration of the delay registers 62 to 65, the multipliers 66 to 68, and the adders 69 and 70 is a digital filter 200.

In FIG. 7, in-phase component data of the sampling frequency fs ′ is input to the interpolator 15 via the input terminal 1. The interpolator 15 converts the input data into a sampling frequency of 2 fs.
The frequency is converted to 'and sent to the filter 17. The filter 17
Removes unnecessary frequency components from the transmitted data and sends it to the terminal of the selector 61. Similarly, orthogonal component data of the sampling frequency fs / 4 is input to the interpolator 16 via the input terminal 2. The interpolator 16 converts the input data to the sampling frequency.
The frequency is converted to 2fs' and sent to the filter 18. The filter 18 removes unnecessary frequency components from the transmitted data and sends the data to the terminal of the selector 61. The selector 61 switches the input in-phase component data and quadrature component data at the frequency fs and alternately outputs the data from the terminal, and sends the data to the delay register 62 and the multiplier 66. For example, when the input of the selector 61 is connected to the orthogonal component data side (terminal), the output (terminal) of the selector 61, the output of the delay shift register 63, and the output of the delay shift register 65 become orthogonal component data, and the delay The output of the shift register 62 and the output of the delay shift register 64 become in-phase component data. Therefore, orthogonal components are input to the multiplier 66, the multiplier 67, and the multiplier 68. Conversely, if the selector 61 is connected to the in-phase component data side (terminal), the multiplier 66, the multiplier 6
7. The quadrature component is input to the multiplier 68. Here, the multiplier 66, the multiplier 67, the multiplier
If the selector 61 is connected to the in-phase component data side, the multiplication coefficient of 68
If 61 is connected to the orthogonal component data side, the selector 71, the selector 72, and the selector 73 are connected so as to select a multiplication coefficient for the orthogonal component. At this time, assuming that the multiplication coefficients on the in-phase component data side are a0, a2, and a4 and the multiplication coefficients on the quadrature component data side are b1, b3, and b5, as in FIG. Matches the output. As mentioned above,
When the sampling frequency is converted to a double frequency (from fs / 2 to fs), the processing conventionally performed separately for the in-phase component and the quadrature component can be realized with one digital filter configuration.

Next, an embodiment which has achieved the fifth object will be described with reference to FIGS. 8, 1 and 2 are input terminals, 4 and 5 are interpolators, 74, 75, 76, 77, 89, 90, 91, 9
2, 93 are delay shift registers, 78, 79, 80, 86, 87, 88
Is a multiplier, 81, 82, 83, 84 and 85 are adders, 201 is a complex coefficient filter, 11 is a D / A converter, and 3 is an output terminal.
FIG. 9 is a diagram for explaining the frequency-amplitude characteristics in FIG. 8, where the horizontal axis represents frequency and the vertical axis represents amplitude, (1) is the frequency characteristic of the input signal of the complex coefficient filter, and (2) is the The frequency characteristics of the filter, (3) is the frequency characteristic of the complex coefficient filter shifted by fs / 4 from the real coefficient filter, and (4) is
(3) is the frequency characteristic of the output signal passing through the filter, and (5) is the output frequency characteristic when the output of the complex coefficient filter is only one signal (real part side). 8, the input terminal 1 is connected to the interpolator 4, and the interpolator 4 is connected to the delay register 74 and the multiplier 78. The delay register 74 is a delay register
74, the delay register 75 connects to a delay register 76 and a multiplier 79. The delay register 76 is connected to a delay register 77, which is connected to a multiplier 80. The input terminal 2 is connected to the interpolator 5, and the interpolator 5 is connected to the delay register 89. The delay register 89 is a delay register
The delay register 90 is connected to a delay register 91. The delay register 91 is connected to a delay register 92 and a multiplier 87, and the delay register 92 is connected to a delay register 93.
Connect to The delay register 93 is connected to a multiplier 88.
The multiplier 78 and the multiplier 86 are connected to an adder 81, and the adder 81 and the multiplier 79 are connected to an adder. The adder
82 and the multiplier 87 are connected to an adder 83, and the adder 83 and the multiplier 80 are connected to an adder 84. The adder 84 and the multiplier 88 are connected to an adder 85, and the adder 85 is a D / A converter.
Connect to 11. The D / A converter 11 is connected to the output terminal 3. Here, delay registers 74 to 80 and 89 to 93 and a multiplier
The configuration of 78 to 80, 86 to 88 and adders 81 to 85 is a complex coefficient filter 201.

The in-phase component data of the sampling frequency fs ′ is input to the interpolator 4 via the input terminal 1. The interpolator 4 frequency-converts the transmitted data to a sampling frequency 2fs' (= fs / 2) and sends the data to the delay register 74 and the multiplier 78. Similarly, orthogonal component data of the sampling frequency fs ′ is input to the interpolator 5 via the input terminal 2. The interpolator 5 converts the transmitted data to a sampling frequency 2fs' (= fs / 2) and sends the data to the delay register 89. The data input to the delay register 74 is delayed by fs / 4 and sent to the delay register 75. The delay register 75 further delays the input data by fs / 4 and sends it to the delay register 76 and the multiplier 79. The data input to the delay register 76 is delayed by fs / 4,
7, the delay register 77 further delays the input data by fs / 4 and sends it to the multiplier 80. The delay register 89
Is delayed by fs / 4 and sent to the delay register 90 and the multiplier 86. The delay register 90 further delays the input data by fs / 4 and sends it to the delay register 91. The data input to the delay register 91 is delayed by fs / 4 and sent to the delay register 92 and the multiplier 87. The delay register 92 further delays the input data by fs / 4 and sends it to the delay register 93.
The delay register 93 delays the input data by fs / 4 and sends it to the multiplier 88. The data sent to the multiplier 78 is multiplied by a multiplication coefficient a0 and sent to the adder 81. The data sent to the multiplier 86 is also multiplied by the multiplication coefficient a1 and sent to the adder 81. 2 input to the adder 81
The two data are added and sent to the adder 82. The data sent to the delay register 79 is multiplied by a multiplication coefficient “−a2” and sent to the adder 82. The adder 82 adds the two data sent and sends the result to the adder 83. The data sent to the delay register 87 has a multiplication factor "-
a3 "is multiplied and sent to the adder 83.
83 adds the two data sent and sends it to the adder 84. The data sent to the delay register 80 is multiplied by a multiplication coefficient “a4” and sent to the adder 84. The adder 84 adds the two data sent and sends the result to the adder 85. The data sent to the delay register 88 is multiplied by a multiplication coefficient “a5” and sent to the adder 85. The adder 85 adds the two data sent and sends the result to the D / A converter 11. The D / A converter 11 converts the transmitted data into analog data, and outputs the data through the output terminal 3 as quadrature-modulated data. The delay shift registers 74, 75, 76, 77, 89, 90, 91, 92, 9
The complex coefficient filter 201 is composed of 3, the multipliers 78, 79, 80, 86, 87, 88 and the adders 81, 82, 83, 84, 85. Here, the frequency characteristic of the input signal of the complex coefficient filter 201 in FIG. 8 is as shown in FIG. 9 (1). However, the required signal is (nfs) ± (fs /
4) It is [n: integer], and other signals (hatched portions in FIG. 9 (1)) are interference signals. To remove this interfering signal, FIG.
A complex coefficient filter shown in FIG. 9 (3) is required in which the frequency characteristic of the real coefficient filter shown in (2) is frequency-shifted by fs / 4. Here, in FIG. 8, since the input signal can be represented as a complex signal, the filter coefficients are represented by complex coefficients.

The frequency characteristic of the original real coefficient filter In the transfer function H (z) for FIG. 9 (2), considering a filter whose frequency is shifted by fa, z = exp (sT) = exp (jωT) = Exp (j2πf / f
s) Therefore, if the frequency is shifted, f′-fa is substituted and z ′ = exp (j2π (f−fa) / fs) = z · exp (−j2πfa / fs) = z · α. That is, the complex coefficient α is applied. Where fa
= Fs / 4, α = -j. Assuming that the original filter is of the FIR type, H (z) = a0 + a1 · z− ¹ + a2 · z− ² +... + An · z− ⁿ (a0 to a
n): Filter coefficient is as follows: H (z) = a0−a2 · z− ² +... + an · z− ⁿ + j · (a1 · z− ¹⁻ a3 · z)
⁻³ +... + An ⁻¹ · z ⁻ⁿ⁻¹ ), and the transfer function has a form in which the real part and the imaginary part are completely separated. In this complex coefficient filter, since the transfer function coefficient is represented by a complex number, the frequency characteristic does not have a symmetrical frequency characteristic with positive and negative frequencies, but has a frequency characteristic that repeats from 0 to fs. That is, the complex coefficient filter can handle a signal having a frequency of 0 to fs, and the band is twice as large as the real signal. FIG. 9 (3) shows the frequency characteristic of the frequency-shifted complex coefficient filter. The output signal of this filter is as shown in FIG.

However, if the output of the complex coefficient filter is only one signal (real part side) as shown in FIG. 8, the positive and negative symmetrical frequency characteristics of the same frequency as the real coefficient filter are shown in FIG. 9 (5).
Can be obtained. As described above, a filter and a quadrature modulator required to convert the sampling frequency to four times the frequency can be configured by one digital filter.

[0057]

As described above, according to the present invention, by performing quadrature modulation using digital signal processing, a gain difference, a phase difference, and a DC offset do not occur between in-phase component data and quadrature component data. Thus, a digital quadrature modulator can be provided.

As a second effect of the present invention, it is possible to provide a digital quadrature modulator whose processing is simplified by replacing a multiplier and an adder required for quadrature modulation with a selector and a sign inverter.

Further, as a third effect of the present invention, the double sampling frequency conversion at the latter stage of the two double sampling frequency conversions does not perform the interpolation process and reduces the number of taps and the operating frequency of the digital filter to one. / 2 can provide a digital quadrature modulator made possible.

Further, as a fourth effect of the present invention, a digital filter capable of forming a double sampling frequency conversion for in-phase component data and a double sampling frequency conversion for quadrature component data with one digital filter. A quadrature modulator can be provided.

As a fifth effect of the present invention, it is possible to provide a filter required for quadrupling the sampling frequency conversion and a digital quadrature modulator which can configure quadrature modulation processing with one digital filter. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a quadrature modulator according to the present invention.

FIG. 2 is a block diagram showing an example of a quadrature modulator according to the present invention.

FIG. 3 is a block diagram showing an example of a quadrature modulator according to the present invention.

FIG. 4 is a block diagram showing an example of a quadrature modulator according to the present invention.

FIG. 5 is a block diagram illustrating an example of a quadrature modulator according to the present invention.

FIG. 6 is a block diagram showing an example of a quadrature modulator according to the present invention.

FIG. 7 is a block diagram showing an example of a quadrature modulator according to the present invention.

FIG. 8 is a block diagram illustrating an example of a quadrature modulator according to the present invention.

FIG. 9 is a diagram showing an amplitude characteristic for explaining an example of the quadrature modulator of the present invention.

FIG. 10 is a block diagram showing an example of a conventional quadrature modulator.

FIG. 11 is a table showing combined data of in-phase component data and quadrature component data in quadrature modulation.

FIG. 12 is a block diagram showing an example of a conventional quadrature modulator.

FIG. 13 is a block diagram showing an example of a quadrature modulator according to the present invention.

FIG. 14 is a block diagram illustrating an example of a quadrature modulator according to the present invention.

FIG. 15 is a block diagram showing an example of a conventional quadrature demodulator.

FIG. 16 is a block diagram illustrating an example of a quadrature demodulator according to the present invention.

FIG. 17 is a block diagram showing an example of a quadrature demodulator according to the present invention.

FIG. 18 is a block diagram illustrating an example of a quadrature demodulator according to the present invention.

FIG. 19 is a block diagram illustrating an example of a quadrature demodulator according to the present invention.

[Explanation of symbols]

1: Input terminal (in-phase component data input terminal of sampling frequency fs / 4) 2: Input terminal (quadrature component data input terminal of sampling frequency fs / 4) 3: Output terminal 4, 5: Interpolator ( 15, 16, 19, 20: Interpolator (frequency 2)
6, 7, 21, 22: Digital filter (operating frequency fs), 17, 18: Digital filter (operating frequency fs)
s / 2), 8, 9, 66, 67, 68: Multiplier, 30, 31, 32, 3
3, 34, 35: multiplier, 46, 47, 48, 49, 50, 51: multiplier, 78, 79, 80, 86, 87, 88: multiplier, 96, 97: multiplier (analog), 10 , 69, 70: adder, 36, 37,
38, 39, 40: adder, 52, 53, 54, 55, 56: adder,
81, 82, 83, 84, 85: adder, 98: adder (analog), 11, 94, 95: D / A converter, 12, 23, 24: selector (switching frequency fs), 61, 71, 72, 73: selector (switching frequency fs), 14: selector (switching frequency fs /
2), 13: sign inverter, 25, 26, 27, 28, 29: delay shift register (operating frequency fs), 41, 42, 43, 4
4, 45: delay shift register (operating frequency fs), 57,
58, 59, 60: delay shift register (operating frequency fs / 2),
62, 63, 64, 65: delay shift register (operating frequency f
s), 74, 75, 76, 77: delay shift register (operating frequency fs), 89, 90, 91, 92, 93: delay shift register (operating frequency fs), 99, 100, 101, 102, 103, 1
04: FIR filter, 111, 116, 117: shift register, 128: oscillator, 129: 90 degree phase shifter, 200: digital filter, 201: complex coefficient filter, 301: input terminal, 302, 303: output terminal, 304 , 305: A / D converter, 306, 307: multiplier, 308, 309: digital filter, 310, 311: adder, 313: 90 degree phase shifter,
314: oscillator, 315: A / D converter, 316, 317, 31
8: shift register of operating frequency fs, 319, 320, 32
1, 322, 323, 324: shift register of operating frequency fs / 4, 325, 326: adder, 327, 328: operating frequency fs
Shift register, 329: clear signal generation circuit,

Claims (19)

[Claims] 1. After the sampling frequency fs 'of two digital data of in-phase component data and quadrature component data is converted to a sampling frequency fs (fs = 4fs'), a carrier frequency fc (fc = fs) is converted. A quadrature modulator for performing quadrature modulation in (/ 4), including one D / A converter, wherein the sampling frequency conversion and quadrature modulation are realized by digital signal processing. 2. A digital quadrature modulator according to claim 1, wherein a digital filter having an operating frequency fs / 2 and a double sampling frequency conversion from a sampling frequency fs / 4 to a sampling frequency fs / 2 are performed. First sampling frequency conversion means;
Second sampling frequency conversion means for performing a double sampling frequency conversion from the sampling frequency fs / 2 to the sampling frequency fs, wherein the first and second sampling frequency conversion means are The sampling frequency fs /
4. A digital quadrature modulator obtained by subjecting the in-phase component data and quadrature component data of No. 4 to a sampling frequency fs. 3. The digital quadrature modulator according to claim 1, wherein the sampling frequency is fs / 4 to fs / 2.
A first sampling frequency conversion means for performing a double sampling frequency conversion to the sampling frequency fs / 2 and a sampling frequency fs
And a second sampling frequency converting means for performing a double sampling frequency conversion to the sampling frequency fs / 4 to perform a double sampling frequency conversion from the sampling frequency fs / 4 to the sampling frequency fs / 2. The first sampling frequency converting means has a first interpolator, a first digital filter having an operating frequency of fs / 2, a second interpolator, and a second digital filter having an operating frequency of fs / 2. The in-phase component data is subjected to sampling frequency conversion by the first interpolator and the first digital filter, and the quadrature component data is subjected to sampling frequency conversion by the second interpolator and the second digital filter. The second sampling frequency conversion means for performing the double sampling frequency conversion from / 2 to the sampling frequency fs is constituted by a third digital filter having an operating frequency fs, and samples the in-phase component data and the quadrature component data. Frequency change Quadrature modulator and performing by the combination of the first and second and third digital filter of. 4. The digital quadrature modulator according to claim 1, wherein the sampling frequency conversion and the quadrature modulation processing are configured using at least one complex coefficient digital filter. 5. The digital quadrature modulation circuit according to claim 1, wherein the transfer function H (Z) is used as means for converting the in-phase component data and the quadrature component data of the sampling frequency fs / 4 to the sampling frequency fs. ) = 1 + Z ^-1 + Z ^-2 + Z ^-3 A digital quadrature modulator characterized by using a digital filter. 6. The digital quadrature modulator according to claim 1, wherein the in-phase component data and the quadrature component data of the sampling frequency fs / 4 are converted into a sampling frequency fs by a sampling frequency. A digital quadrature modulator comprising a shift register having an operation frequency of fs / 4 and a selector and a sign inverter as a circuit for performing the quadrature modulation. 7. The digital quadrature modulator according to claim 1, wherein the transfer function H (Z) is used as means for converting the in-phase component data and the quadrature component data of the sampling frequency fs / 4 to the sampling frequency fs. ) = (1 + Z ^-1 + Z ^-2 + Z ^-3 ) A digital quadrature modulator characterized by using ^two digital filters. 8. The digital quadrature modulator according to claim 1, wherein the in-phase component data and the quadrature component data at the sampling frequency fs / 4 are converted into a sampling frequency fs by a sampling frequency conversion circuit. A digital quadrature comprising a combination of a shift register having an operation frequency of fs / 4, a shift register having an operation frequency of fs, and an adder, and a circuit for performing the orthogonal modulation using a selector and a sign inverter. Modulator. 9. A quadrature modulator according to claim 1, wherein a first interpolator for interpolating in-phase component data at a sampling frequency fs / 4, and data interpolated by said first interpolator are sampled at a sampling frequency. a first digital filter that converts the sampling frequency to fs, a first multiplier that multiplies the data subjected to the sampling frequency conversion by the first digital filter by cos (2 · π · fc · t), A second interpolator for interpolating the orthogonal component data of the normalized frequency fs / 4, a second digital filter for converting the data interpolated by the second interpolator to a sampling frequency fs, A second multiplier for multiplying the data subjected to sampling frequency conversion by the second digital filter by sin (2 · π · fc · t), and the data multiplied by the second multiplier and the first multiplication Multiplied by the filter , And D which converts the data added by the adder into analog data.
/ A converter, and converts the sampling frequency fs 'of the two digital data of the in-phase component data and the quadrature component data into a sampling frequency fs (fs = 4fs'), and then converts the carrier frequency fc A digital quadrature modulator, wherein quadrature modulation is performed at (fc = fs / 4). 10. The quadrature modulator according to claim 1, wherein
A first interpolator for interpolating the in-phase component data at the sampling frequency fs / 4, a first digital filter for converting the data interpolated by the first interpolator to a sampling frequency fs, A second interpolator for interpolating the orthogonal component data of the sampling frequency fs / 4, a second digital filter for converting the data interpolated by the second interpolator to a sampling frequency fs, And the data subjected to sampling frequency conversion by the first digital filter and the data subjected to sampling frequency conversion by the first digital filter are input and output alternately at a frequency fs / 2 cycle. A first switch for performing a sign inversion of the data output by the first switch, a data whose sign is inverted by the sign inverter, and a first switch. A second switch for alternately outputting the two data inputted and inputted at a cycle of a frequency fs / 4, and a data outputted by the second switch. A D / A converter for converting analog data into analog data, and converting a sampling frequency fs 'of two digital data of in-phase component data and quadrature component data into a sampling frequency fs (fs = 4fs') A digital quadrature modulator that performs quadrature modulation at a carrier frequency fc (fc = fs / 4) after the modulation. 11. The quadrature modulator according to claim 1, wherein
A first interpolator for interpolating the in-phase component data of the sampling frequency fs / 4, a first digital filter for converting the data interpolated by the first interpolator to a sampling frequency fs / 2, , A first FI for interpolating data that has been subjected to sampling frequency conversion by the first digital filter.
An R digital filter, a second interpolator for interpolating the orthogonal component data of the sampling frequency fs / 4, and a second interpolator for converting the data interpolated by the second interpolator to a sampling frequency fs / 2. Two digital filters, a second FIR digital filter for interpolating the data sampled and frequency-converted by the second digital filter, the data filtered by the second FIR digital filter, and the first FIR digital filter. A first switch for alternately outputting the two data inputted and filtered at a cycle of a frequency fs / 2, and encoding the data outputted by the first switch. A sign inverter to be inverted, data whose sign is inverted by the sign inverter, and data output by the first switch. A second switch for inputting data and alternately outputting the input two data at a cycle of a frequency fs / 4, and a D / A for converting data output by the second switch into analog data. And a sampling frequency fs ′ of two digital data of in-phase component data and quadrature component data.
A digital quadrature modulator characterized by performing sampling frequency conversion to (fs = 4fs ′) and then performing quadrature modulation at a carrier frequency fc (fc = fs / 4). 12. The quadrature modulator according to claim 1, wherein
A first interpolator for interpolating the in-phase component data of the sampling frequency fs / 4, a first digital filter for converting the data interpolated by the first interpolator to a sampling frequency fs / 2, A second interpolator for interpolating orthogonal component data having a sampling frequency fs / 4, and a second digital filter for converting the data interpolated by the second interpolator to a sampling frequency fs / 2. And the two data input and input with the data subjected to the sampling frequency conversion by the second digital filter and the data subjected to the sampling frequency conversion by the first digital filter,
A first switch that alternately outputs at a cycle of a frequency fs / 2, an FIR digital filter that interpolates data output by the first switch, and a code that inverts the sign of the output data of the FIR digital filter An inverter, a second switch for inputting the output data of the sign inverter and the output data of the FIR digital filter, and alternately outputting the input two data at a cycle of a frequency fs / 4; And a D / A converter for converting data output by the two switchers into analog data. The sampling frequency fs' of two digital data of in-phase component data and quadrature component data is converted to a sampling frequency fs ( fs = 4fs ′), and then the carrier frequency fc (fc = fs)
A digital quadrature modulator characterized by performing quadrature modulation in / 4). 13. The quadrature modulator according to claim 1, wherein
A first interpolator for interpolating the in-phase component data at the sampling frequency fs / 4 to a four-fold sampling frequency fs, and a sampling frequency fs / 4
A second interpolator for interpolating the quadrature component data into a quadrupled sampling frequency fs, the quadrature component data interpolated to a quadrupled sampling frequency fs by the second interpolator, and the first interpolator An FIR digital filter for inputting two data of in-phase component data interpolated to a four-fold sampling frequency fs and performing quadrature modulation processing, and converting data subjected to quadrature modulation processing by the FIR digital filter into analog values After converting the sampling frequency fs 'of the two digital data of the in-phase component data and the quadrature component data into the sampling frequency fs (fs = 4fs'), A digital quadrature modulator which performs quadrature modulation at a frequency fc (fc = fs / 4). 14. A digital quadrature demodulator which outputs a digital quadrature detection signal by digital signal processing after digitally converting an analog quadrature amplitude modulation signal,
The carrier frequency of the analog quadrature amplitude modulation signal is fIF
The sampling frequency of the digital conversion is fs, and the frequency fC of the quadrature local oscillation signal used for quadrature detection is fs = 4 · fIF, and fc = fs / 4. A digital quadrature demodulator for converting a sampling frequency from fs to fs / 4. 15. The digital quadrature demodulator according to claim 14, wherein the means for performing the sampling frequency conversion includes:
A digital quadrature demodulator using a digital filter of transfer function H (Z) H (Z) = 1 + Z ^-1 + Z ^-2 + Z ^-3 . 16. The digital quadrature demodulator according to claim 14, wherein the means for performing the sampling frequency conversion includes:
A digital quadrature demodulator characterized by using a digital filter of transfer function H (Z) H (Z) = (1 + Z ^-1 + Z ^-2 + Z ^-3 ) ² . 17. The digital quadrature demodulator according to claim 14, 15, 15 or 16, wherein the circuit for performing quadrature detection and sampling frequency conversion has a 4-tap F-mode.
A digital quadrature demodulator having an IR digital filter and having a coefficient of 1, 0, or -1. 18. The quadrature modulator according to claim 14, wherein an A / D converter for digitally converting the quadrature modulated data of the sampling frequency fs / 4, and cos digitally converted by the A / D converter. (2 · π · fc · t), and a sampling frequency fc of the data multiplied by the first multiplier is set to a sampling frequency fs (fs = 4 · t).
fc), a second multiplier for multiplying the digital-converted data by sin (2 · π · fc · t), and a data multiplied by the second multiplier. Is changed to the sampling frequency fs (fs =
And a second digital filter for converting the data output from the first digital filter into quadrature detection of the data output from the first digital filter and the data output from the second digital filter. Quadrature demodulator. 19. The quadrature demodulator according to claim 14, wherein: an A / D converter for digitally converting quadrature modulated data having a sampling frequency fs / 4; and delaying the data digitally converted by the A / D converter. A first shift register having an operating frequency fs, a second shift register having an operating frequency fs for delaying data delayed by the first shift register, and a delay circuit for delaying data delayed by the second shift register. A third shift register having an operating frequency fs, a first adder for receiving data delayed by the first shift register and subtracting data delayed by the first shift register;
And a fourth shift register having an operating frequency fs / 4 for delaying the data subtracted by the adder, and subtracting the data digitally converted by the A / D converter from the data delayed by the second shift register. Second
And a fifth shift register having an operating frequency fs / 4 for delaying the data subtracted by the second adder, and the data output by the first fourth shift register A quadrature demodulator characterized by performing quadrature detection on data output by the second fifth shift register.