JP2625696B2 - SSB modulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a digitally processed SSB modulation circuit and an SSB demodulation circuit. [Summary of the Invention] The present invention performs sampling of a modulation signal at a sampling frequency of 1/2 ⁿ of a carrier frequency, performs baseband processing such as 90 ° phase shift, and uses linear interpolation to change the sampling frequency to a carrier frequency. By converting the frequency to four times the frequency, the modulation of the carrier wave and the synthesis of the modulated wave are equivalent to the data selection and sign inversion processing, and an SSB modulation circuit and an SSB demodulation circuit by a simple digital processing are obtained with a simple configuration. It is like that. 2. Description of the Related Art SSB (single sideband) signals are mainly used for long-distance communication in the shortwave band because they have no carrier components, have good power efficiency, and have a narrow bandwidth and a large number of lines. In order to obtain an SSB signal by analog processing, (i) separating only one sideband from a double-sideband signal using a bandpass filter, (ii) using two balanced modulators and a phase demultiplexer, (Iii) performing multi-stage modulation using a low-frequency subcarrier and a high-frequency carrier, and separating only one sideband using a filter; And various other methods are known. [Problems to be Solved by the Invention] In the generation of the SSB signal by the analog processing as described above, a crystal filter having a steep characteristic in a high frequency region must be used as a bandpass filter. A duplexer cannot be obtained easily,
Multi-stage modulation has problems such as a complicated configuration.
Along with analog processing, there are problems such as stability, reproducibility, and difficulty in adjustment. Therefore, the present applicant has disclosed in Japanese Patent Laid-Open No. 57-84462,
The CCD filter was used as a Hilbert transform filter instead of the phase demultiplexer, and the configuration was simplified by appropriately selecting the phase of the sampling clock.
An SSB modulation circuit using a sampling frequency as a carrier frequency has already been proposed. However, since the proposed circuit includes an analog processing part, the above-mentioned problems such as stability and reproducibility still remain. By the way, with the development of LSI technology in recent years, it has become possible to realize a function equivalent to analog modulation using digital operation. Regarding the generation of an SSB signal by digital signal processing, for example, a Weaver method has been proposed (see US Proc. IRE, December 1956). In a digital SSB modulator, after an analog modulated signal is converted into a digital signal sequence by sampling and quantization, all signal processing is performed by digital operation using a digital filter or the like. The SSB modulation circuit based on the Weaver method is basically configured as shown in FIG. 7, for example. In FIG. 7, a modulated signal having a spectrum as shown in FIG. 8I is supplied in common to the first and second multipliers (11) and (12) from an input terminal 1N, for example, a subcarrier frequency of 2 kHz. It is multiplied (modulated) by the cosine and sine waves of f _SC , respectively. Since the subcarrier is within the band of the baseband input signal, as shown in FIGS.
The output of 1) has the same phase in the upper and lower sidebands, and the output of the multiplier (12) has the upper and lower sidebands in opposite phases and overlap each other. The outputs of the multipliers (11) and (12) have a phase difference of 90 ° from each other. The outputs of both multipliers (11) and (12) are digital low-pass filters (13) with a cutoff frequency of 2 kHz.
And (14) are supplied to third and fourth multipliers (15) and (16). Both multipliers (15) and (16) have
A cosine wave and a sine wave (substantial carrier) having a frequency (f _C -2) [kHz] of the difference between the carrier frequency of f _C [kHz] and the sub-carrier frequency of 2 kHz are supplied, respectively. The sine wave is multiplied by the outputs of the low-pass filters (13) and (14), respectively, and the outputs of the third and fourth multipliers (15) and (16) are shown in FIGS. 8C and D, respectively. Thus, the spectrum is such that the outputs of the low-pass filters (13) and (14) are arranged below the nominal carrier of f _C [kHz]. The negative phase components of the outputs of the multipliers (15) and (16) are canceled by the adder (17), and the output of the adder (17) has a carrier frequency of f _C [kHz] as shown in FIG. ]
SSB signal. In FIG. 7, the frequency of the sub-carrier and the frequency of the carrier, 2 kHz and (f _C
-2) If it is configured to replace [kHz], an SSB demodulation circuit can be obtained. Further, in this specification, for the sake of simplicity, a substantial carrier is also simply referred to as a “carrier”, and is distinguished and described only when particularly necessary. By the way, in the weaver modulation circuit of FIG.
For multiplication of the carrier and the baseband signal in the subsequent stage of the multiplier (15) or the like, the sampling frequency f _SP data of the baseband signal, the carrier frequency, to be precise, the nominal carrier frequency f _C and subcarrier frequency f Frequency f _C of difference from _SC
The frequency conversion must be performed at least twice as large as −f _SC ≡f _C ^* . In other words, the data must be interpolated. However, the data of the baseband signal, that is, the output of the digital low-pass filter (13), together with the baseband signal shown by the thick line in FIG. Sampling frequency of D converter
signal component is present that accompany the fundamental and harmonics of f _SP. Although this accompanying component must be removed by an interpolation filter (digital filter) not shown, f _C ^* >> f
_Since it is _SP , an extremely narrow band low-pass filter is required as an interpolation filter, which is not only difficult to realize, but also
Also in the SSB demodulation circuit, there is a problem that it is difficult to realize easily by all digital processing. In view of the above, the object of the present invention is relatively simple in configuration and can be easily realized by all digital processing.
An SSB modulation circuit and an SSB demodulation circuit are provided. [Means for Solving the Problems] The present invention relates to a first half of ⁿ (n is a natural number) of the carrier frequency.
An analog-to-digital converter for converting an analog modulated signal into a digital signal at a sampling frequency of, a first baseband subcarrier and a 90 ° relative to the first baseband subcarrier. A baseband signal processing means for obtaining a pair of baseband signals by providing a modulator for modulating a second baseband subcarrier having a phase difference with an output of the A / D converter; A pair of sampling frequency converting means for converting the first sampling frequency of the output of the signal processing means into a second sampling frequency four times the carrier frequency by linear interpolation, and a pair of sampling frequency converting means; Selecting means for alternately selecting each output of the means at twice the carrier frequency; and sign inverting means for alternately inverting the sign of the output of the selecting means at the carrier frequency. Out Which is the SSB modulation circuit to obtain a SSB signal into an analog signal. [Operation] According to this configuration, data selection and sign inversion are performed.
This is equivalent to the modulation of a carrier by a baseband signal and the synthesis of a modulated carrier, and SSB modulation by all digital processing is realized with a simple configuration. Embodiment Hereinafter, the present invention will be described with reference to FIGS.
An embodiment of the SSB modulation circuit will be described. FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 7 are denoted by the same reference numerals, and a part of the description will be omitted. In FIG. 1, the baseband subcarrier (frequency f
_SC ) is supplied from the oscillator (18) directly to one multiplier (11) and to the other multiplier (12) via a 90 ° phase shifter (19). The analog modulated signal is supplied to the AD converter (20), and the output of the AD converter (20) is supplied to both multipliers (11) and (12) in common. (21) and (31) denote interpolation filters having the same configuration. Corresponding portions of both interpolation filters (21) and (31) are denoted by the same reference numerals, and redundant description is omitted. I do. The output of one multiplier (11) is supplied via a low-pass filter (13) to a delay circuit (22) and a subtractor (23) of an interpolation filter (21) in common. The output is supplied to the adder (24), and is supplied to the subtractor (23) in a subtractive manner. The output of the subtracter (23) is supplied to the adder (24) via the coefficient multiplier (25). You. The output of the adder (24) is supplied to one register (26). Similarly, the output of the other multiplier (12) is supplied to the other register (36) via the low-pass filter (14) and the interpolation filter (31). The outputs of both registers (26) and (36) are supplied to fixed contacts (41a) and (41b) of an electronic changeover switch (41), respectively. The movable contact (41c) of the switch (41) is connected to one input terminal of an exclusive OR (EXOR) circuit (42) as a sign inverting circuit, and the output of the EXOR circuit (42) is D-
The signal is supplied to the A converter (43), and the output of the DA converter (43) is led out to the output terminal OUT. A clock pulse having a frequency of 4f _C ^* is supplied from the generator (44) to the DA converter (43) and the first 分 frequency divider (45), and the output of the frequency divider (45) is The switch (41) is supplied as a control signal and a second 1/2 frequency divider (46)
Supplied to The output of this divider (46) is connected to the EXOR circuit (4
2) is supplied to the other input terminal and is also supplied to the 1 / ²ⁿ frequency divider (47), and the output of the frequency divider (47), that is, the frequency is
The sampling clock of f _SP is supplied to the AD converter (20). In this embodiment, the frequency division ratio of the 1 / ²ⁿ frequency divider (47) is
When n = 3, the total frequency division ratio of the frequency dividers (45) to (47) is set to 1/32. Next, the operation of the interpolation filter will be described with reference to FIGS. The delay time τ of the delay line (22) of the interpolation filter (21) is set to τ = 1 / f _SP = 2 ⁿ / f _C ^* , and the delay line (2
The difference of the preceding data X _i-1 and subsequent data X _i of the input side and the output side of the 2) (X _i-1 -X _i) is obtained, which coefficients of the coefficient multipliers (25) to k = 1/2 ^m is multiplied. In this embodiment, since k = 1/32 and m = 5, data is actually shifted by 5 bits. The output (X _i-1 −X _i ) / 32 of the coefficient multiplier (25) is the adder (2
Although is added to the preceding data X _i-1 in 4), the adder (24) for operating at a sampling frequency of ^{_{32f SP (= 4f C *)}} , in its output, as shown in Figure 2 , between both data X _i-1 and X _i are linearly interpolated by the interpolation data. The output of the adder (24) is sequentially supplied to a register (26).
Reset by When this linear interpolation calculation is considered as a digital filter, the filter coefficient has an impulse response as shown in FIG. FIG. 4 shows the frequency characteristics of the interpolation filter. In FIG. 4, the frequency axis is normalized at 32f _SP .
As apparent from FIG. 4, the valley portions of the frequency characteristic of the interpolation filter is so consistent with the fundamental and harmonics of the sampling frequency f _SP, supra unnecessary as shown in FIG. 9 Accompanying components can be sufficiently removed. Next, multiplication with a carrier will be described with reference to FIG. By the sampling frequency conversion by the linear interpolation described above, the sampling frequency of the data output from both registers (26) and (36) becomes four times the carrier frequency f _C ^* . Therefore, the sampling timing is appropriately adjusted, and the data of the cosine wave having the frequency f _C ^* to be supplied to the multiplier (15) in the latter stage of FIG. 7 is as shown in FIG. 5A. And [1],

[0], [-1],

Similarly, sine wave data having a frequency f _C ^* to be supplied to the multiplier (16) shown in FIG. 7 can be considered as shown in FIG. 5B.

[0], [1],

[0], [-1]... In the modulation process, the two-phase carrier wave

Since the data of [0] is unnecessary, a switch (4 ⁾ whose switching frequency is switched to a control signal of 2f _C ^* as shown in FIG. 5C is controlled.
According to 1), two-phase carrier data [1] and [−
At the timing [1], the output data of both registers (26) and (36) is selected. Note that the carrier data is

At the timing of [0], the interpolation filters (21) and (31) may be respectively deactivated. The data of 2's complement display selected by the switch (41) is
It is supplied to the EXOR circuit (42). As shown in FIG. 5D, the EXOR circuit (42) receives the carrier data of FIGS.
The output of the frequency divider (46) which becomes " _Hi " at the timing of [1] is supplied, whereby the sign of the data selected by the switch (41) is inverted (the binary code of the data is (1) is added to the LSB. Thus, in this embodiment, by selecting a sampling frequency of 4f _C ^* , quadrature modulation and synthesis of a carrier can be performed with a simple configuration of the selection switch (41) and the sign inversion circuit (42). The cost of the semiconductor device used is reduced. In the above-described embodiment, the substantial carrier frequency f _C ^* has been described as the difference between the nominal carrier frequency f _C and the sub-carrier frequency f _SC , but may be, of course, the sum f _C + f _SC of both frequencies. Further, the conversion ratio of the sampling frequency is not limited to the above-described embodiment, and can be appropriately set to a power of two. For example, if the carrier frequency is set near the lower limit of the short wave band, f _C ^* ≒ 3M
Be selected in Hz, Setting the sampling frequency f _SP ≒ 12 kHz, the conversion ratio reaches 2 ^10. Further, the present invention can be similarly applied to an SSB modulation circuit based on a phase synthesis method. In this case, instead of the multiplication circuits (11) and (12) of the embodiment of FIG. 1, a Hilbert filter for 90 ° phase shift in the base band is used, and the output of this Hilbert filter is a low-pass filter. (1
Via 3) and (14), the interpolation filters (21) and (3)
1), and thereafter, an SSB signal is obtained in the same manner as in the embodiment of FIG. In this case, unlike the embodiment of FIG. 1, not a multi-stage modulation, the reference sampling frequency is the nominal carrier frequency f _C. The SSB signal according to the embodiment shown in FIG. 1 is demodulated by using an SSB demodulation circuit as shown in FIG. In FIG. 6, the analog SSB of the nominal carrier frequency f _C
A signal is supplied from an input terminal 1N to an AD converter (51),
The output of the AD converter (51) is supplied to the movable contact (53c) of the electronic changeover switch (53) via the sign inverting circuit (52). Frequency 4f _C ^* clock pulse generator (54)
Are supplied to an A / D converter (51) and a first 1/2 frequency divider (55). The output of the frequency divider (55) is supplied to a switch (53) as a control signal, and 2 1/2 divider (5
6) supplied to. The output of the frequency divider (56) is supplied to the inverting circuit (52) and also to the 1 / ²ⁿ frequency divider (57). Outputs of the fixed contacts (53a) and (53b) of the switch (53) are supplied to thinning circuits (61) and (62), respectively, and outputs of the thinning circuits (61) and (62) are multipliers (63) and (62). 64) respectively. A subcarrier having a frequency of f _SC is supplied from the oscillator (65) directly to one multiplier (63) and to the other multiplier (64) via a 90 ° phase shifter (66). , The outputs of the multipliers (63) and (64) are combined by an adder (67) and supplied to a DA converter (68). The DA converter (68) includes a frequency divider (5
From 7), the pulse is supplied as a sampling clock of a pulse having a frequency of f _SP = f _C ^* / ²ⁿ . The sign of the output data of the A / D converter (51) is inverted by the sign inverting circuit (52) at the same timing as in the EXOR circuit (42) of FIG. It is alternately distributed to the thinning circuits (61) and (62). In the thinning circuits (61) and (62),
The sampling frequency of the input data is 4f by the signal processing reverse to the interpolation filters (21) and (31) of FIG.
Is converted from _C ^* to ^{_{f SP = f C * / 2}} n. Both thinning circuits (6
The outputs of (1) and (62) are the multipliers (63) and (6), respectively.
After the synchronous detection in 4), the signals are combined by the adder (67) and supplied to the DA converter (68), where the DA converter (6) is used.
From 8), the analog demodulated signal is led to the output terminal OUT. [Effects of the Invention] As described above in detail, according to the present invention, the carrier frequency
Since the modulation signal was sampled at a sampling frequency of 1/2 ⁿ and baseband processing such as 90 ° phase shift was performed, the sampling frequency was converted to four times the carrier frequency using linear interpolation. Modulation of a carrier wave and synthesis of a modulated wave can be performed by data selection and sign inversion processing, and an SSB modulation circuit with a simple configuration and all digital processing can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment using an SSB modulation circuit according to the present invention, and FIGS. 2 to 4 are conceptual diagrams and characteristics for explaining the operation of the main part of the embodiment of FIG. FIG. 5 is a time chart for explaining the operation of another main part of the embodiment, FIG. 6 is a block diagram showing the configuration of an SSB demodulation circuit for explaining the present invention, FIG. FIG. 8 shows a conventional
FIG. 9 is a block diagram showing a configuration example of the SSB modulation circuit and a spectrum diagram for explaining its operation, and FIG. 9 is a spectrum diagram for explaining the present invention. (11) and (12) are multipliers, (18) is a subcarrier oscillator,
(19) is a 90 ° phase shifter, (20) is an AD converter, (21),
(31) is an interpolation filter, (41) is a selection switch, (42)
Is a sign inversion circuit, (43) is a DA converter, (44) is a sampling clock generator, f _C is a nominal carrier frequency, f _C ^*
Is the effective carrier frequency.

Claims (4)

(57) [Claims] A first frequency of 1/2 ⁿ (n is a natural number) of a carrier frequency;
An analog-to-digital converter that converts an analog modulated signal into a digital signal at a sampling frequency of: a first baseband subcarrier and a first baseband subcarrier that is 90 ° relative to the first baseband subcarrier. A baseband signal processing means for obtaining a pair of baseband signals by providing a modulator for modulating a second baseband subcarrier having a phase difference with the output of the A / D converter; A pair of sampling frequency converting means for converting the first sampling frequency of the output of the processing means into a second sampling frequency four times the carrier frequency by linear interpolation, respectively; Selecting means for alternately selecting each output of the converting means at twice the carrier frequency; and sign inverting means for alternately inverting the sign of the output of the selecting means at the carrier frequency. Means digital An SSB modulation circuit, which converts a digital output to an analog signal to obtain an SSB signal. 2. The SSB modulation circuit according to claim 1, wherein a multiplication circuit is used as said modulator. 3. The SSB modulation circuit according to claim 1, wherein a Hilbert filter is used as said modulator. 4. An A / D converter for converting an SSB modulated signal into a digital signal based on a frequency signal four times the carrier frequency, and a digitized signal from the A / D converter is alternately inverted at the carrier frequency. A pair of thinning circuits for converting the sampling frequency of input data from the carrier frequency of 4 times to 1/2 ⁿ (n is a natural number) of the carrier frequency, and a signal from the sign inverting circuit. Selecting means for alternately supplying the pair of decimation circuits at a frequency twice as high as the carrier frequency; and a subcarrier of the first baseband and a subcarrier of the first baseband relative thereto. And a subcarrier generating means for generating a second baseband subcarrier having a phase difference of 90 °, and synchronously detecting each output from the pair of decimation circuits with the first baseband subcarrier. One demodulation means, the other demodulation means for synchronously detecting each output from the pair of decimation circuits with the second baseband subcarrier, and the output signals from the one and other demodulation means are added. An SSB demodulation circuit comprising: an adding unit; and a DA converter that converts an output from the adding unit into an analog signal using a frequency signal of 1/2 ⁿ of the carrier frequency.