JPH08149167A - Digital orthogonal modulator - Google Patents

Abstract

PURPOSE: To obtain a modulation signal having a frequency equivalent to 1/4 of a highest processing speed of a D/A converter. CONSTITUTION: The digital orthogonal modulator is made up of a digital orthogonal modulation circuit comprising band limit filters 1, 2, 9, 10, polarity inverters 54, 55, 57, 58, and parallel-serial converters 56, 59, a digital adder 17, a D/A converter 18, a low pass filter 19, an analog mixer 20, and a band pass filter 21 without using a ROM providing the output of cosine and sine waveform signals and a digital multiplier different from a conventional digital orthogonal modulator. Thus, a modulation signal whose frequency is equivalent to 1/4 of a highest processing speed of the D/A converter 18 is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital quadrature modulator used for radio equipment such as digital mobile communication.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing the structure of a conventional digital quadrature modulator of this type. For example, the number of baseband I and Q signals is 2, and the I1 signal is
(23), Q1 signal (24), I2 signal (35), and Q2 signal (36). In FIG. 2, 1, 2, 9, and 10 are baseband I,
Digital band limiting filters (hereinafter referred to as DBPFs) for band limiting Q signals, 3, 4, 11 and 12 are band limited baseband I, Q signals 25, 26, 37, 38 and carrier signals (COS waveform signals). 30, 42, SIN waveform signal 31, 4
Digital multiplier for multiplying 3), 5, 13 are counters for calling SIN waveform signals 31, 43 and COS waveform signals 30, 42, 6 and 14 are COS waveform generation ROMs for outputting COS waveform signals 30, 42, 7, 15 is a SIN waveform generation ROM that outputs SIN waveform signals 31 and 43, and 8 and 16 are I and Q signals 32 and 3
Digital adder for adding 3, 44, 45, 17 is a digital quadrature modulation signal output from the digital quadrature modulation circuit 3
A digital adder for adding 4, 46, a D / A converter for converting a multi-carrier signal 47 into an analog modulated signal 49, a low pass filter (LPF) for removing unnecessary frequency components of the analog modulated signal 49, 20 Is a low pass filter
(LPF) An analog mixer 50 that mixes an analog signal 50 output from a local oscillator (LO) with a local oscillation signal 51 and up-converts it, and 21 removes unnecessary frequency components of an analog signal 52 output from the analog mixer 20. Band pass filter (BPF).

The operation of the digital quadrature modulator configured as described above will be described. First, baseband I1
The signal (23) and the baseband Q1 signal (24) are DB
It is input to the PFs 1 and 2 and the band is limited. Next, the band-limited baseband I1 signal (25) and baseband Q1 signal (26) are input to the digital multipliers 3 and 4, respectively.

The clock 1 (27) is input to the counter 5, and the control signal 28, 29 is output from the counter 5. These control signals 28 and 29 are COS waveform generation R, respectively.
Input to OM6 and SIN waveform generation ROM7
The COS waveform signal 30 and the SIN waveform signal 31 are output from M6 and 7, respectively, and the digital multipliers 3 and 4 are output.
Is input to Band-limited baseband I1 signal (2
5) and the COS waveform signal 30 are multiplied by the digital multiplier 3, and the I signal 32 is output.

The band-limited baseband Q1 signal (26) and the SIN waveform signal 31 are multiplied by the digital multiplier 4 and a Q signal 33 is output. Next, the I signal 32 and the Q signal 33 are added by the digital adder 8 and the digital quadrature modulation signal 34 is output.

Similarly, the baseband I2 signal (35),
The baseband Q2 signal (36) is the DBPF 9 and 10 respectively.
Is input to and the band is limited. Next, the band-limited baseband I2 signal (37) and baseband Q2 signal (38) are
Input to the digital multipliers 11 and 12, respectively.

The clock 2 (39) is input to the counter 13, and the counter 13 outputs control signals 40 and 41. The control signals 40 and 41 are generated by the COS waveform generation R, respectively.
Input to OM14 and SIN waveform generation ROM15, this RO
C14 waveform signal 42 and SIN waveform signal 43 are output from M14 and M15, respectively, and the digital multipliers 11 and 12 are respectively output.
Is input to Band-limited baseband I2 signal (3
7) and the COS waveform signal 42 are multiplied by the digital multiplier 11, and the I signal 44 is output.

The band-limited baseband Q2 signal (38) and the SIN waveform signal 43 are multiplied by the digital multiplier 12 and a Q signal 45 is output. Next, the I signal 44 and the Q signal 45 are added by the digital adder 16, and the digital quadrature modulation signal 46 is output.

Next, the digital quadrature modulated signals 34 and 46 are added by the digital adder 17 to obtain a multi-carrier signal.
47 is obtained.

Next, the multi-carrier signal 47 is a D / A converter.
An analog modulated signal 49 is obtained at the timing of the sampling clock 48 when input to 18. Analog modulation signal
An unnecessary frequency component of 49 is removed by a low pass filter (LPF) 19, and an analog signal 50 is obtained. This analog signal 50 is input to the analog mixer 20, and the local oscillator
A local oscillation signal 51 from (LO) is mixed and up-converted to obtain an analog signal 52. Finally, the analog signal 52 is input to the bandpass filter (BPF) 21 and the unnecessary frequency components are removed, whereby the analog modulated signal 53 is obtained.

[0011]

The modulated signal output from the above-described conventional digital quadrature modulator is generally mixed with the local oscillation signal from the local oscillator in the subsequent stage and up-converted to obtain the necessary signal component. The others are filtered out. However, as the frequency of the modulation signal decreases, a steep filter is required, and it becomes difficult to realize the filter. Therefore, it is necessary to increase the frequency of the modulation signal output from the digital quadrature modulator.

However, the frequency of the modulation signal output by the digital quadrature modulator is determined by the operation speed of the digital multiplier. In the digital quadrature modulator having the above configuration, when the number of samplings per cycle is 4, the frequency of the modulation signal is 1 which is the maximum operation speed of the digital multiplier.
There was a drawback that / 4 was the limit.

The present invention solves the above-mentioned conventional drawbacks, and an object of the present invention is to provide a digital quadrature modulator capable of outputting a modulated signal having a quarter frequency of the maximum processing speed of a D / A converter. Is.

[0014]

In order to solve the above problems and to achieve the object, the present invention uses a digital band limiting filter for band limiting baseband I and Q signals, a polarity inverter and a parallel-serial converter. A digital quadrature modulation circuit configured, a digital adder for adding output signals of the digital quadrature modulation circuit, a D / A converter for converting the digital modulation signal into an analog modulation signal, and an unnecessary frequency component of the analog modulation signal From a low-pass filter that removes, an analog mixer that up-converts the analog signal output by the low-pass filter by mixing it with a local oscillation signal, and a band-pass filter that removes unnecessary frequency components of the analog signal output by the analog mixer. From the output of the bandpass filter Wherein the obtaining a grayed modulated signal.

[0015]

According to the present invention, the present invention does not use a ROM or a digital multiplier that outputs COS and SIN waveform signals as in the conventional digital quadrature modulator, and the present invention provides a band limiting filter, a polarity inverter and a parallel converter. According to the present invention, the digital quadrature modulator including the serial converter, the digital adder, the D / A converter, the low-pass filter, the analog mixer, and the band-pass filter constitutes the digital quadrature modulator. Since the number of oversamplings of the carrier per cycle is 4, it is possible to output a modulated signal having a frequency of 1/4 of the maximum processing speed of the D / A converter.

[0016]

1 is a block diagram showing the configuration of a digital quadrature modulator according to an embodiment of the present invention. The number of baseband I and Q signals is 2, and the I1 signal 2
3, Q1 signal 24, I2 signal 35, and Q2 signal 36. In FIG. 1, 54, 55 and 57, 58 are polarity inverters for inverting the polarities of input signals, and 56, 59 are for synthesizing signals inputted in four systems in time order and converting them into signals of one system. It is a parallel-serial converter (hereinafter referred to as a P / S converter). The blocks, signals and the like having the same functions described in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. Here, the polarity inverters 54, 55, 57, 58
And the P / S converters 56 and 59 form a digital quadrature modulation circuit.

The operation of the digital quadrature modulator configured as above will be described.

The baseband I1 signal (23) and the baseband Q1 signal (24) are band-limited by the digital band limiting filters (DBPF) 1 and 2, respectively, and the baseband I1 signal (25) and the base are band-limited, respectively. A band Q1 signal (26) is obtained.

This band-limited baseband I1 signal
(25) and the baseband Q1 signal (26) are polarity-inverted by the polarity inverters 54 and 55, respectively, and the -I signal 60 and
A -Q signal 61 is obtained. On the other hand, the outputs from the four systems of the baseband I1 signal (25), the baseband Q1 signal (26) and the -I signal 60, -Q signal 61, which are band-limited by the DBPFs 1 and 2, are input to the P / S converter 56. To be done. These signals are combined in time order by the P / S converter 56 at the timing of the cycle of clock 1 (27), and the digital quadrature modulation signal is obtained.
DATA (nT) 34 is obtained. This digital quadrature modulated signal DA
TA (nT) is as shown in (Equation 1).

[0020]

[Equation 1] However, n; 0,1,2, ..., k = 0,1,2, ..., T; 1 /
Similarly to the cycle of the clock 1, the baseband I2 signal (35) and the baseband Q2 signal (36) are band-limited by the DBPFs 9 and 10, respectively, and the baseband I2 signal (37) and the baseband Q2 are band-limited. A signal (38) is obtained.

This band-limited baseband I2 signal
(37) and the baseband Q2 signal (38) are polarity-inverted by the polarity inverters 57 and 58, respectively, and -I signal 62 and
A Q signal 63 is obtained. On the other hand, the outputs from the four systems of the baseband I2 signal (37), the baseband Q2 signal (38) and the -I signal 62, -Q signal 63 which are band-limited by the DBPFs 9 and 10 are input to the P / S converter 59. To be done. These signals are combined in time order by the P / S converter 59 at the timing of the cycle of the clock 2 (39) to obtain a digital quadrature modulation signal.
DATA (nTT) 46 is obtained. This digital quadrature modulation signal D
ATA (nTT) is as shown in (Equation 2).

[0022]

[Equation 2] However, n; 0,1,2, ..., k = 0,1,2, ..., T; 1 /
Period of clock 2 Next, the digital quadrature modulation signals 34 and 46 are digital adders.
The addition is performed by 17 to obtain the multi-carrier signal 47.

Next, the multi-carrier signal 47 is a D / A converter.
An analog modulation signal 49 is obtained at the timing of the sampling clock 48 when input to 18.

An unnecessary frequency component is removed from the analog modulated signal 49 by a low pass filter (LPF) 19 to obtain an analog signal 50. The analog signal 50 is input to the analog mixer 20, mixed with a local oscillation signal 51 from a local oscillator (LO) and up-converted to obtain an analog signal 52. Finally, the analog signal 52 is input to the bandpass filter (BPF) 21 and the unnecessary frequency component is removed, whereby the analog modulated signal 53 is obtained.

As described above, according to the present invention, the baseband I,
A digital band limiting filter for band limiting the Q signal,
A digital quadrature modulation circuit composed of a polarity inverter and a P / S converter, a digital adder for adding the output signals of the digital quadrature modulation circuit, and a D / A converter for converting the digital modulation signal into an analog modulation signal. A low-pass filter for removing unnecessary frequency components of the analog modulated signal, an analog mixer for up-converting the analog signal output by the low-pass filter with a local oscillation signal, and an analog signal output by the analog mixer. By constructing a digital quadrature modulator from a bandpass filter that removes unnecessary frequency components and constructing a digital quadrature modulator without using a ROM or a digital multiplier, in the present invention, the number of oversamplings per carrier cycle is increased. Since 4 is set to D / A It can be realized digital quadrature modulator capable of obtaining a modulated signal of 1/4 of the frequency of the maximum processing speed of the vessel.

For example, when the number of operation bits is 10 bits, the maximum processing speed of the current general commercially available 10-bit digital multiplier is about 40 MHz, and the modulation frequency is limited to about 10 MHz in the conventional configuration. However, the general market 10
Since the maximum processing speed of the bit D / A converter is about 400 MHz, the modulation frequency can be 100 MHz in the present invention, and a modulation signal with a frequency about 10 times that of the conventional configuration can be obtained.

[0027]

As described above, the present invention provides a band limiting filter, a digital quadrature modulation circuit composed of a polarity inverter and a P / S converter, a digital adder, and a D / A converter. , A low-pass filter, an analog mixer, and a band-pass filter form a digital quadrature modulator, and a digital quadrature modulator without using a ROM or a digital multiplier, the maximum processing speed of the D / A converter is obtained. The effect is that a modulated signal having a frequency of 1/4 can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital quadrature modulator according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional digital quadrature modulator.

[Explanation of symbols]

1, 2, 9, 10 ... Digital band limiting filter (DBP
F), 17 ... Digital adder, 18 ... D / A converter,
19 ... Low pass filter (LPF), 20 ... Analog mixer, 21 ... Band pass filter (BPF), 23, 35 ...
Baseband I signal, 24, 36 ... Baseband Q signal,
25, 37 ... Band-limited baseband I signal, 26,
38 ... Band-limited baseband Q signal, 27, 39 ... Clock, 34, 46 ... Digital quadrature modulation signal, 47 ... Multi-carrier signal, 48 ... Sampling clock, 4
9, 53… Analog modulation signal, 50… Analog signal from which unnecessary frequency components of analog modulation signal are removed, 51… Local oscillation signal, 52… Analog signal up-converting analog signal, 54,55,57,58… Polarity inversion Bowl, 56, 59
... Parallel-serial (P / S) converter, 60, 62 ...- I
Signal, 61, 63 ...- Q signal.

Claims (1)

[Claims] 1. A digital band limiting filter for band limiting a baseband I signal and a baseband Q signal, a digital quadrature modulation circuit composed of a polarity inverter and a parallel-serial converter, and an output of the digital quadrature modulation circuit. A digital adder for adding signals, a D / A converter for converting a digital modulation signal into an analog modulation signal, a low-pass filter for removing unnecessary frequency components of the analog modulation signal, and an analog signal output by the low-pass filter Is composed of an analog mixer for up-converting by mixing with a local oscillation signal and a bandpass filter for removing unnecessary frequency components of the analog signal output by the analog mixer, and an analog modulation signal is obtained from the output of the bandpass filter. Characteristic digital direct Intermodulator.