JPH0964702A - Clock multiplier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the clock multiplier with a configuration simply built in even a monolithic digital integrated circuit. SOLUTION: The clock multiplier is provided with an edge pulse generating circuit 13 receiving an input clock signal whose period is T and converting the signal into a pulse whose pulse width is narrower than T/4 and providing its output, three delay circuits 14, 15, 16 whose delay time is set respectively to be T/4, 2T/4, 3T/4 and receiving a pulse respectively and providing an output of delayed pulse, and a synthesis circuit that synthesizes the pulse outputted from the edge pulse generating circuit 13 and the three delayed pulses outputted respectively from the three delay circuits and provides an output of a multiple signal being a multiple of 4 of the clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock multiplier for multiplying a clock signal in, for example, a semiconductor integrated circuit,
In particular, it relates to its configuration.

[0002]

2. Description of the Related Art A conventional clock multiplier is disclosed in, for example, "Handbook of Institute of Electronics, Information and Communication Engineers", 1st edition, 1st edition (March 30, 1988) edited by Institute of Electronics, Information and Communication Engineers, p. 543-
A non-linear diode, as described in 544,
It is composed of a bandpass filter and the like. An AC signal is input from the input terminal, the current waveform is distorted by the nonlinear characteristics of the diode to generate harmonics, and a harmonic component of a specific order is selected from the harmonics with a bandpass filter,
The multiplication operation was performed by outputting.

[0003]

In the conventional clock multiplier as described above, a bandpass filter, which is an analog circuit, is required in the circuit configuration in order to select and extract the harmonic components. There is a problem that it is very difficult to incorporate in an integrated circuit.

Therefore, it has been desired to realize a clock multiplier which can be easily incorporated in a monolithic digital integrated circuit.

[0005]

A clock multiplier according to the present invention inputs a clock signal having a period T and converts it into a pulse having a width narrower than T / n (where n is an integer of 2 or more). And an edge pulse generation circuit for outputting the delay time T / n, 2T / n, ..., (n-1) .T / n, respectively.
And n-1 delay circuits that are input with each pulse and output a delay pulse, and the pulses output from the edge pulse generation circuit and the n-1 delay circuits output from the n-1 delay circuits, respectively. And a delay circuit for synthesizing the delayed pulse of ## EQU1 ## and outputting a multiplied signal obtained by multiplying the clock signal by n. Since it is composed of a logic circuit rather than an analog circuit, it can be easily incorporated in a monolithic digital integrated circuit.

Further, the clock multiplier according to the present invention has delay times of T / n, 2T / n, ..., (n-1) .multidot.
T / n (where n is an integer of 2 or more), each of which inputs a clock signal with a period T and outputs a delayed clock signal from n−1 delay circuits and n−1 delay circuits N-1 delayed clock signals output respectively,
Alternatively, n edge pulse generation circuits for inputting clock signals, converting them into pulses having a width narrower than T / n, and outputting the pulses, and n number of the aforementioned edge pulse generation circuits respectively output from the n edge pulse generation circuits. And a synthesis circuit for synthesizing the pulses and outputting a multiplied signal obtained by multiplying the clock signal by n.
Since it is composed of a logic circuit rather than an analog circuit, it can be easily incorporated in a monolithic digital integrated circuit.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. FIG. 1 shows a fourth embodiment of the present invention.
It is a block diagram which shows the structure of the clock multiplier of multiplication.
Reference numeral 11 is a clock input terminal, 12 is a multiplied clock output terminal, 13 is an edge pulse generation circuit, 14 to 16 are delay circuits, and 17 is an OR circuit. The OR circuit 17 synthesizes the pulses output from the edge pulse generation circuit 13 and the delay circuits 14 to 16 and outputs the synthesized pulse.

FIG. 2 is a diagram showing an example of the circuit configuration of the edge pulse generating circuit 13. Reference numeral 21 is an input terminal, 22 is a pulse output terminal, 23 is an inverter, 24 is an odd number of inverter rows, and 25 is a NOR circuit. Clock input terminal 1
The clock signal input from 1 is input terminal 21 as it is.
Is input to The clock signal input to the input terminal 21 is output in the inverter 23 with its polarity reversed. The input signal passed through the inverter 23 is input to the odd numbered inverter rows 24 and the NOR circuit 25. The signal input to the odd-numbered inverter row 24 passes through the odd-numbered inverter row 24 and then is input to the NOR circuit 25. Therefore, the signal that has passed through the inverter row 24 is the NOR circuit 25 as much as it passes through the inverter row.
Is input to the NOR circuit 25 with the same polarity as when it was input from the input terminal 21 because it is delayed and is passed through an odd number of stages of inverters. The NOR circuit 25 outputs a signal having a pulse width corresponding to the time difference between the signal directly input to the NOR circuit 25 and the signal input to the NOR circuit 25 after passing through the inverter rows 24 of odd stages. To be done.

FIG. 3 is a diagram showing an example of the circuit configuration of the delay circuits 14-16. The delay circuit can be realized by a circuit in which buffers are connected in series. Reference numeral 31 is an input terminal, 32 is a delayed signal output terminal, and 33 is a buffer array. The pulse output from the edge pulse generation circuit 13 is input to the input terminal 31. It takes time for the input pulse to pass through the buffer train 33. This required time becomes the delay time, and the delayed pulse is output from the delay signal output terminal 32. The delay time can be easily adjusted by increasing or decreasing the number of buffers in the buffer array 33 according to the time to delay.

FIG. 4 is a waveform diagram of the input or output of the constituent means according to the first embodiment of the present invention. CLKIN is
The signal input from the clock input terminal 11 and CL
KOUT is the waveform of the signal output from the multiplied clock output terminal 12. OP13, OP14, OP15 and OP16 are outputs of the edge pulse generating circuit 13 and the delay circuits 14, 15 and 16, respectively. The input clock signal has a clock frequency of 250 MHz (cycle 4n
s). The delay times of the delay circuits 14, 15 and 16 are 1 ns, 2 ns and 3 ns, respectively, and the edge pulse generation circuit 13 generates a pulse corresponding to the rising edge of the input signal, and the pulse width is 500 ps.
(0.5 ns).

When a clock signal having a clock frequency of 250 MHz is input from the clock input terminal 11, the edge pulse generating circuit 3 outputs a pulse having a pulse width of 500 ps. The output pulse is the OR circuit 17 and the delay circuit 1.
4, 15 and 16 respectively. Delay circuit 1
Since the delay time of 4 is 1 ns, the pulse output from the delay circuit 14 is input to the OR circuit 17 with a delay of 1 ns from the pulse directly input to the OR circuit 17.
Similarly, since the delay time of the delay circuit 15 is 2 ns, the pulse output from the delay circuit 15 is ORed with a delay of 2 ns from the pulse directly input to the OR circuit 17.
It is input to the circuit 17. Moreover, since the delay time of the delay circuit 16 is 3 ns, the pulse output from the delay circuit 16 is 3 n longer than the pulse input directly to the OR circuit 17.
It is input to the OR circuit 17 with a delay of s.

The output gate is the OR circuit 1.
Therefore, all the pulses input to the OR circuit 17 pass through the gate and are output. The clock frequency output to the multiplied clock output terminal 12 through the OR circuit 17 is 1 GHz (cycle 1 ns), and a clock signal that is four times the original clock frequency is output.

In the clock multiplier configured as described above, the clock can be multiplied without using an analog circuit to form a circuit, so that the multiplier can be easily incorporated in a monolithic digital integrated circuit.

Embodiment 2 FIG. FIG. 5 is a block diagram showing the configuration of a 4 × clock multiplier according to the second embodiment of the present invention. 51 is a clock input terminal similar to 11, 5
Reference numeral 2 is a multiplied clock output terminal similar to 12, 53 to 55 are delay circuits similar to 14 to 16, 56 to 59 are edge pulse generating circuits similar to 13, and 60 is an OR circuit similar to 17.

FIG. 6 is a waveform chart of the input or output of the constituent means according to the second embodiment of the present invention. CLKIN is
Signal input from the clock input terminal 51, CL
KOUT is the waveform of the signal output from the multiplied clock output terminal 52. OP53, OP54 and OP55 are outputs of the delay circuits 53, 54 and 55, respectively. OP56, OP57, OP58, and OP59 are edge pulse generation circuits 56, 57, 58, and 59, respectively.
Is the output of. As in the first embodiment, the input signal has a clock frequency of 250 MHz (cycle 4 ns).
The delay time of each of the delay circuits 53, 54 and 55 is 1n.
s, 2 ns, and 3 ns, and the edge pulse generation circuits 56 to 59 generate a pulse corresponding to the input signal, and the pulse width thereof is 500 ps (0.5 ns).

When a clock signal with a clock frequency of 250 MHz is input from the clock input terminal 51, the clock signal is an edge pulse generating circuit 56 and a delay circuit 53, 5.
4 and 55. Edge pulse generation circuit 56
Generates a pulse having a pulse width of 500 ps, and the pulse is input to the OR circuit 60. Further, since the delay time of the delay circuit 53 is 1 ns, the clock signal output from the delay circuit 53 is input to the edge pulse generation circuit 57 later than the clock signal input to the edge pulse generation circuit 56 by 1 ns. It Edge pulse generation circuit 57
Outputs to the OR circuit 60 a pulse having a pulse width of 500 ps, which is 1 ns later than the pulse output by the edge pulse generation circuit 56. Similarly, since the delay time of the delay circuit 54 is 2 ns, the clock signal output from the delay circuit 54 is delayed by 2 ns with respect to the clock signal input to the edge pulse generation circuit 56, and then input to the edge pulse generation circuit 58. Is entered. The edge pulse generation circuit 58 is
2n more than the pulse output from the edge pulse generation circuit 56
A pulse having a pulse width of 500 ps delayed by s is ORed by the OR circuit 6
Output to 0. The delay time of the delay circuit 55 is 3 ns.
Therefore, the clock signal output from the delay circuit 55 is input to the edge pulse generation circuit 59 later than the clock input to the edge pulse generation circuit 56 by 3 ns. The edge pulse generation circuit 59 outputs to the OR circuit 60 a pulse having a pulse width of 500 ps which is 3 ns later than the pulse output by the edge pulse generation circuit 56.

The output gate is the OR circuit 6.
Since it is 0, all the pulses input to the OR circuit 60 pass through the gate and are output. The clock frequency output to the multiplied clock output terminal through the OR circuit 60 is 1G.
Hz (cycle 1 ns), and a clock signal having a frequency four times the original clock frequency is output.

In the clock multiplier configured as described above, the circuit can be constructed without using an analog circuit and the clock can be multiplied. Therefore, the multiplier can be easily incorporated in a monolithic digital integrated circuit.

Embodiment 3 FIG. It should be noted that in the above-described embodiment, the pulse of 4 multiplication is generated, but the present invention is not limited to this, and the multiplication number can be changed. At this time, it is necessary to adjust the pulse width generated by the edge pulse generation circuits 13 and 56 to 59, and increase or decrease the number of delay circuits or edge pulse generation circuits according to the multiplication number.

Further, in the above-mentioned embodiment, the edge pulse generating circuits 13 and 56 to 59 are exemplified by the configuration by the inverter, but the present invention is not limited to this and has other similar functions. For example, a buffer or the like may be used. Furthermore, a configuration may be adopted in which a clock signal is input with a delay difference provided between the two-input exclusive OR gates. Also, the delay circuits 14 to 16 and 53
The same applies to .about.55, and one having another similar function, for example, an even number of stages of inverters may be used, or a capacitive load may be added at the time of output.

[0021]

As described above, according to the present invention, an analog circuit is not required to form a circuit, and a clock multiplier can be configured by a logic circuit. Therefore, a monolithic digital integrated circuit can be used. Can be easily incorporated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a clock multiplier of 4 multiplication according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a circuit configuration of edge pulse generation circuits 13 and 56 to 59.

FIG. 3 is a diagram showing an example of a circuit configuration of delay circuits 14 to 16 and 53 to 55.

FIG. 4 is a waveform diagram of input or output of the configuration means according to the first exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a 4 × clock multiplier according to a second embodiment of the present invention.

FIG. 6 is a waveform diagram of input or output of the configuration means according to the second exemplary embodiment of the present invention.

[Explanation of symbols]

 11, 51 Clock input terminal 12, 52 Multiplied clock output terminal 13, 56-59 Edge pulse generation circuit 14-16, 53-55 Delay circuit 17, 60 OR circuit 21, 31 Input terminal 22 Pulse output terminal 23 Inverter 24 Odd stage Inverter array 25 NOR circuit 32 Delayed signal output terminal 33 Buffer array

Claims (2)

[Claims] 1. An input clock signal having a period T is input, and T
/ N, an edge pulse generating circuit that converts and outputs a pulse having a width narrower than n (n is an integer of 2 or more), and delay times are T / n, 2T / n, ..., (n-
1) .T / n, n-1 delay circuits that respectively input the pulses and output delayed pulses, the pulses output from the edge pulse generation circuit, and the n-1 N output from each delay circuit
-1 and the delayed pulse are combined to generate a clock signal n
A clock multiplier comprising: a synthesizing circuit that outputs a multiplied signal. 2. The delay time is T / n, 2T / n,
, (N−1) · T / n (where n is an integer of 2 or more), and n−1 delay circuits that input the input clock signals of the cycle T and output the delayed clock signals, respectively. , N− that are respectively output from the n−1 delay circuits
N delayed edge pulse signals, or n edge pulse generation circuits for inputting each of the input clock signals, converting the pulses into a pulse having a width narrower than T / n, and outputting the n edge pulse generation circuits And a combining circuit for combining n pulses output from each circuit and outputting a multiplied signal obtained by multiplying a clock signal by n.