JPS60130219A - Digital analog converter - Google Patents

Abstract

PURPOSE:To obtain an analog converting output with low cost and high quality by changing a stepwise output waveform by a D/A converter into a slow waveform through linear approximation while using a low-order LPF. CONSTITUTION:Digital data sampled and coded by a prescribed sampling frequency is converted into a step-shaped signal A of a level in response to each code by the D/A converter and sampled D, E by sampling signals B, C phase- shifted by T/2. Then a signal F from a substractor 13 is integrated (G) by an integration device 14, the result is added to a hold output E of a sample-and- hold circuit 12 and an analog signal output is obtained via an LPF16. Since generation of spurious radiation is decreased, the LPF of the next stage is enough for less number of stages.

Description

[Detailed Description of the Invention] 艮QiQ9') Regarding an analog converter, in particular, a digital converter that suppresses spurious components based on the ring frequency and performs the 42 function. It concerns analog converters.

The analog conversion output from the GTJ converter generally contains spurious components caused by the lean-pulling frequency.A high-order LPF (low-pass filter) is used to remove this spurious component. However, this method degrades the phase characteristics of the analog output signal and impedes high-quality analog signal reproduction (rI
It's coming.

Therefore, a method is used in which the sampling frequency is multiplied several times to move the spurious to a higher frequency band, and the order of the IP used is changed even if the order is low.

FIG. 1 shows a schematic block diagram of a digital-to-analog converter using such a method. 4-8. By covering in this way, the spurious component is shifted to a higher frequency band Δ.

B
This is an analog signal. As a result, the spurious component' has a high frequency L, so l PF
3 means that even if a low-order one with good phase characteristics is used, the spurious may be sufficiently suppressed.

However, this method has the drawback that the scale of the arithmetic unit 1 becomes large, which causes an increase in performance.

The present invention has been made to eliminate the above-mentioned drawbacks of the prior art, and its purpose is to provide a low-cost, high-quality analog conversion output using a low-order +PF. Our objective is to provide a digital-to-analog converter that can be used to obtain the desired results.

The digital-to-analog converter according to the present invention has a digital input coded with a predetermined ring-ring period (
Fi';''', converting means into a stepped signal of a level corresponding to each code;
means for generating a step signal delayed by approximately 1/2 of the sampling period, means for dividing the difference signal between these two step signals 8 into 11'1, and converting the integrated output into the delayed step signal. The added output is outputted as an analog signal through a low-pass filter.

fruitful example Next, an embodiment of the present invention will be explained using FIG.

Digital data sampled at a predetermined sampling frequency and assimilated is converted by a D/Δ] converter 10 into a stepped signal having a level corresponding to each code. This conversion signal (Δ) is converted into two sample bold circuits 1
1.12 and each limp ring signal (B), (C
), respectively. Both sample and hold outputs (D>, (F) become two inputs of the 1I11n circuit 13, and the result of the attenuation is the input of the integrator 14. This integral output (G) and the hold output (E) of the →J' sample bold circuit are the two inputs of the adder 15. This crimping output (Figure 1) is derived via the l-P F 16 and becomes an analog output (7M output).

Timing controller 17 is sample hold circuit 1
1.12 sampling signals (B) and (C), and also controls the operation timing of the D/A converter 1O and the operation timing of the integrator 14.

Figure 3) ~ (1'') are the various parts of the device in Figure 2 (△
) to (11) are shown correspondingly (1-3),
D7/△=' Suppose that the stepped output of the converter 10 has a waveform like (△), and the sampling signals are (B) and (C), respectively.
) of j: It is assumed that the phase is shifted by T/2 from the sea urchin. Here, T indicates the limp ring circumference ++U when digital human power 1r+S'j is converted into g. As a result, the output of each sample and hold circuit 11.12 is <D>,
(E) becomes a step-like signal waveform that is out of phase with each other by T/2, and the output becomes ()- of (). Vessel 1/LJ:
(If the integral operation of this differential output (') is reset to reset 1 at the falling timing of the sampling pulse (B), then this integral output tit, (G)
So, the addition output by Ijn etc. λ; ) is a suppressed signal waveform.

Therefore, when inputting -C1 such a signal (+-1>), 1-P
[1G(j) 6 is good for a simple circuit configuration of low order.

Since the step-like waveform after the inverter is converted into an almost gently sloped waveform by linear approximation, there is less spurious noise compared to the step-like steep 7-j pulse-like waveform. Ingredients will be less. Therefore, the limp ring pulses (B), (C) of 1J sample hold circuit 11.12
It is not necessary that the phase difference between T y'2 and J is approximately T/
2. If J: (, 1o also sample hold circuit 1
1. Use Serinobu circuit instead of using 1.12. Te (D)
, (F) may be generated.

Effects According to the present invention, as in the Song Dynasty, the step-like output waveform of the D/△l inverter is converted into a gentle waveform by linear approximation, which reduces the generation of spurious and makes it suitable for the next stage LPF. If the order is low, J:<, therefore, the circuit has a simple configuration and is a low-cost device.Since it is passed through a low-order IPF, there is no phase deterioration of the analog signal.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a conventional digital-to-analog converter, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an operational waveform diagram of the blocks in FIG. 2. Explanation of symbols of main parts 11.12...Sample and hold circuit 13...
...Subtractor 1/l...Integrator 15...Constrictor 16...l-P F Applicant: Pioneer Co., Ltd.1 Agent: Patent attorney Ii Motohiko Rimura (1 other person)

Claims (1)

[Claims] means for converting a digital input signal encoded by a predetermined lean-blend cycle to stepwise levels corresponding to each code; The time is approximately 1/2 of the period (J-delayed step-like pattern (i1). A digital analog-to-log converter having means for adding to a stepped signal, and outputting the added output through a low-pass filter.