JPH04150111A - D/a conversion method - Google Patents

Abstract

PURPOSE:To eliminate second harmonics component having been unavoidable in a conventional D/A conversion method by adopting this method such that a center position of a synthesized pulse output has always a prescribed phase difference with respect to a timing signal. CONSTITUTION:An input digital signal 1 inputted synchronously with a timing signal 6 is converted into parallel signals 31, 32 corresponding to a prescribed pulse waveform by ROMs 8, 9. Then a parallel/serial converter 4 applies parallel/serial conversion to parallel signals 31, 32 outputted from the ROMs 8, 9 by a timing signal 6 and a clock signal 7 to convert the signals 31, 32 into pulse outputs 41, 42. Then the pulse outputs 41, 42, are given to a subtractor 10, in which they are subtracted, thereby allowing the digital signal 1 to be PWM- converted into a synthesis pulse output 11. In this case, the center position of the synthesis pulse output 11 always has a prescribed phase difference with respect to the timing signal 6. Thus, no second harmonics are produced in the synthesis pulse output 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital signal converter that converts digital signals into analog signals.
The present invention relates to a conversion method A, and particularly relates to a method using PWM conversion.

PWM conversion is used as one of the conventional D/A conversion methods, but this method generally causes harmonic distortion.

An example of a conventional D/A conversion method using a PWM converter will be described below with reference to the drawings.

FIG. 6 is a block diagram showing the configuration of a conventional D/A conversion method. In FIG. 6, 1 is an input digital signal, 2 is a ROM that stores a pulse waveform corresponding to the input digital signal 1, and 4 is for converting parallel signal output 3 of ROM 2 from parallel to serial to output a pulse output 5. This is a parallel-to-serial converter. 6 is a timing signal synchronized with the input digital signal 1, and 7 is a clock signal that determines the resolution of the pulse.

A conventional D/A conversion method performed with the above configuration will be described below with reference to FIGS. 6, 7, and 8.

FIG. 7 shows the input digital signal 1, pulse output 6, and clock signal 7 in FIG. It shows the relationship with the timing signal 6, and FIG. 8 shows the relationship with the input digital signal 1.
and timing signal 6. Clock signal 7. 5 is a diagram showing the timing with pulse output 5. FIG. First, as shown in FIG. 7, the pulse output 5 for each input digital signal 1 is
The center position of each line coincides with the rising edge of the timing signal 6, and is symmetrical with respect to the center position. Further, the rising edge and falling edge of each pulse output 5 are synchronized with the rising edge of the clock signal 7. Therefore, in the example shown in FIG.
The frequency of the cuff lock signal 7 required for WM conversion is at least 12 times the sampling frequency of the input digital signal 1.

Next, the operation of each part will be explained with reference to FIG. As shown in FIG. 8, an input digital signal 1 input in synchronization with a timing signal 6 is converted by the ROM 2 into a parallel signal 3 corresponding to a pulse waveform as shown in FIG. Then, in the parallel-to-serial converter 4, the timing signal 6 and the clock signal 7 are used to convert the parallel output from the ROM 2 into a parallel-to-serial output 5. As a result, FIGS. The input digital signal 1 is PWM-converted into a pulse output 5 as shown in FIG.

Problems to be Solved by the Invention However, the signal D/A converted by such a method contains harmonic distortion components. This situation will be explained below using FIG. 9.

In Fig. 9, the solid line in (a) is the original analog signal before being converted to a digital signal, and ('b) is the digital signal obtained by A/D converting the analog signal shown in (,) using the conventional D/A. This is a pulse that has been PWM converted using the conversion method.

Here, the pulse shown in (g)) is divided into a signal component (C) with a duty of % and a signal component (d) with bipolarities. As a result, (b) does not have any distortion components, but (d
), the positive polarity pulse and the negative polarity pulse 7 are asymmetrical. Therefore, in the signal obtained by passing the pulse shown in (b) through a low-pass filter, the positive and negative waveforms are asymmetrical, as shown by the dotted line (-), and second harmonics are generated.

As described above, in the conventional D/A conversion method, there remains the problem that second harmonics are generated by PWM conversion in principle, regardless of the characteristics of the analog elements at the subsequent stage. Also, when the sampling frequency of the input digital signal is high, PW
There is a problem in that the frequency of the lock signal required for M conversion becomes very high. The present invention addresses these problems and provides an A conversion method that does not generate such second-order harmonics even when PWM conversion is performed, and it is possible to perform PWM conversion at a lower clock frequency than conventionally. The purpose is to provide the following.

Means for Solving the Problems In order to solve the above-mentioned problems, the D/A conversion method according to the present invention converts an input digital signal that is taken in in synchronization with a timing signal so that the first change point thereof is relative to the timing signal. A first pulse that always has a constant phase difference and whose second change point changes according to the value of the human input digital signal, and the first change point is the first change in the first pulse. a second pulse whose position is the same as that of the point, and whose second change point changes according to the complement of the input digital signal, and performs a predetermined operation on the first pulse and the second pulse. The pulses are synthesized through processing to output a synthesized pulse, and the center position of the output of the synthesized pulse is configured to always have a constant phase difference with respect to the timing signal.

Function As described above, the D/A conversion method of the present invention
The output of the composite pulse that combines these pulse outputs has a center position that always has a constant phase difference with respect to the timing signal, and a positive polarity pulse and a negative polarity pulse with the same absolute value. Since they are vertically symmetrical to each other, secondary harmonics are not generated in principle in the output of the composite pulse. Furthermore, compared to the conventional D/A conversion method, the lock frequency required for PWM conversion is halved.

Embodiment Hereinafter, a D/A conversion method according to an embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a D/A conversion method according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an input digital signal 1 in FIG.
, the relationship between the pulse output 41, the clock signal 7, and the timing signal 6.

In addition, FIG. 3 shows the input digital signal 1 in FIG.
Pulse output 42. The relationship between a clock signal 7 and a timing signal 6 is shown. In FIG. 1, parallel-to-serial converter 4. Timing signal 6 is the same as that in FIG. ROM5 and ROM9 in FIG. 1 have input/output relationships as shown in FIGS. 2 and 3. Further, 10 is a subtracter for subtracting the outputs 41 and 42 of the individual parallel-to-serial converters 4, and outputs a composite pulse output 11.

The D/A conversion method according to the embodiment of the present invention configured as described above will be explained below with reference to FIGS. 1, 2, 3, and 4.

FIG. 4 shows input digital signal 1 and timing signal 6. 4 is a diagram showing the timing of the clock signal 7, the pulse outputs 41, 42 of the individual parallel-to-serial converters 4 and the composite pulse output 11; FIG.

First, the operation of each part will be explained with reference to FIG. The input digital signal 1 inputted in synchronization with the timing signal 6 is transmitted to the ROMB and ROM ca as shown in FIGS. 2 and 3.
Parallel signal 3 corresponding to the pulse waveform shown in the figure
1.32. and a timing signal 6 and a clock signal 7 in each parallel-to-serial converter 4.
YOFI, convert the parallel signals 31 and 32 output from ROM8 and ROM9 from parallel to serial, respectively,
Convert to pulse specific force 41.42. Then, by subtracting the individual pulse outputs 41 and 42 by the subtracter 10, the input digital signal 1 is converted to the composite pulse output 11 as PW.
M-converted.

To explain this situation using the timing chart shown in FIG. It changes depending on the value of digital signal 1. and pulse output 4
The power center of the composite pulse output 11 obtained by subtracting the pulse output 42 from 1 is synchronized with the rising edge of the timing signal 6.

Next, FIG. 5 shows the pulse output 41 for each input digital signal 1. FIG. 2 is a diagram showing the relationship between Parnu-roki 429 and composite pulse output 11; Using FIG. 6, the waveform of the composite pulse output 11 for each input digital signal 1 will be analyzed. First, Figure 5 (-).

As shown in (b), the pulse output 41. Pulse output 4
2 always have the same position of the rising edge, and by changing the position of the falling edge, the pulse becomes a pulse corresponding to each input digital signal 1 and a signal whose polarity is inverted.

As shown in FIG. 5(C), the positions of the rising and falling edges of the composite pulse output 11 obtained by subtracting the pulse output 42 from the pulse output 41 are the falling edges of the pulse output 41 and 42. determined by the position of As a result, the composite pulse output 11 has a bipolar component p, and since the positive polarity pulse and the negative polarity pulse, which have the same absolute value, are vertically symmetrical to each other, in principle, the second harmonic is generated. Does not occur.

In addition, as shown in FIGS. 2 and 3, the pulse output 41
．． 42, its power center (temporal center of the rising edge and falling edge of each value of input digital signal 1) does not have to be constant, so the seventh
Compared to the conventional example shown in the figure, the frequency of the clock signal 7 may be half.

In this embodiment, the positions of the rising edges of pulse output 41 and pulse output 42 are the same, and pulse output 41.
The period when 42 is at high level is the period when input digital signal 1
and its complement.

Note that the D/A conversion method according to this embodiment has a pulse output of 4
1 and the falling edge of the pulse output 42 are at the same position, or the rising edge of the pulse output 41 and the falling edge of the pulse output 42 are at the same position, or the pulse output 41 The configuration is such that the falling edge of the pulse output 42 and the rising edge of the pulse output 42 are at the same position, and the period during which the pulse outputs 41 and 42 are at a low level corresponds to the input digital signal 1 and its complement. However, there is no guarantee that the same effect can be obtained.

Effects of the Invention As described above, the D/A conversion method according to the present invention converts input digital signals taken in synchronization with timing signals into
A first pulse whose first changing point always has a constant phase difference with respect to the timing signal and whose second changing point changes according to the value of the input digital signal, and the first changing point is converted into a second pulse whose timing is the same as the first changing point of the first pulse, and whose second changing point changes according to the complement of the input digital signal, and which is different from the first pulse. By combining the second pulse and the second pulse through predetermined arithmetic processing and outputting a composite pulse, the center position of the composite pulse output always has a constant phase difference with respect to the timing signal. D
It becomes possible to eliminate second-order harmonic components, which are inevitable in the /A conversion method. Furthermore, the lock frequency required for PWM conversion can also be reduced to half.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a D/A conversion method according to a first embodiment of the present invention, and FIG. A waveform diagram showing the relationship between the output, the clock signal, and the timing signal, and FIG. 3 shows the input digital signal, the second pulse output, the clock signal, and the timing in the D/A conversion method of the first embodiment of the present invention. Waveform diagram showing the relationship with the signal,
FIG. 4 is a timing chart of each signal in the D/A conversion method of the first embodiment of the present invention, and FIG. 5 shows pulse waveforms of various parts in the D/A conversion method of the first embodiment of the present invention. A waveform diagram, FIG. 6 is a block diagram showing a conventional D/A conversion method, and FIG. 7 shows the relationship between an input digital signal, a clock signal, and a timing signal in a conventional D/A conversion method. Waveform diagram, Figure 8 is conventional D/A
Timing chart diagram of each signal in the conversion method, No. 9
The figure is a waveform diagram showing waveform distortion of a reproduced waveform when a conventional D/A conversion method is used. 2.8.9...ROM, 4...Parallel-serial converter, 1Q...Subtractor. Name of agent: Patent attorney Akira Okaji and others 26 Figure λnozuichital signal! Noderus output 71 + 41 Tin diagram λ Kazai digital m'gF / Pulse output D42 Ward can

Claims (5)

[Claims] (1) An input digital signal that is taken in in synchronization with a timing signal is such that its first change point always has a constant phase difference with respect to the timing signal, and its second change point is the same as that of the input digital signal. The first value changes depending on the value.
and a second pulse whose first change point is at the same position as the first change point of the first pulse, and whose second change point changes according to the complement of the input digital signal. The first pulse and the second pulse are combined by predetermined calculation processing to output a composite pulse, and the center positions of adjacent change points of the output of the composite pulse are A D/A conversion method characterized by always having a constant phase difference with respect to a timing signal. (2) a first changing point of the first pulse is a rising edge from a low level to a high level; a second changing point of the first pulse is a falling edge from a high level to a low level; and the first changing point of the second pulse is a rising edge from a low level to a high level, and the second changing point of the second pulse is a falling edge from a high level to a low level. 2. The D/A conversion method according to claim 1, wherein the predetermined arithmetic processing is subtraction. (3) the first changing point of the first pulse is a falling edge from a high level to a low level, and the second changing point of the first pulse is a rising edge from a low level to a high level; and the first changing point of the second pulse is a falling edge from a high level to a low level, the second changing point of the second pulse is a rising edge from a low level to a high level, and the The D/A conversion method according to claim 1, characterized in that the predetermined arithmetic processing is subtraction. (4) a first changing point of the first pulse is a rising edge from a low level to a high level; a second changing point of the first pulse is a falling edge from a high level to a low level; and the first changing point of the second pulse is a falling edge from a high level to a low level, the second changing point of the second pulse is a rising edge from a low level to a high level, and the The D/A conversion method according to claim 1, characterized in that the predetermined arithmetic processing is addition. (5) a first changing point of the first pulse is a falling edge from a high level to a low level; a second changing point of the first pulse is a rising edge from a low level to a high level; and the first changing point of the second pulse is a rising edge from a low level to a high level, the second changing point of the second pulse is a falling edge from a high level to a low level, and the The feature is that the predetermined calculation process is addition.
A D/A conversion method according to claim 1.