JPH0295940U - - Google Patents
Info
- Publication number
- JPH0295940U JPH0295940U JP458389U JP458389U JPH0295940U JP H0295940 U JPH0295940 U JP H0295940U JP 458389 U JP458389 U JP 458389U JP 458389 U JP458389 U JP 458389U JP H0295940 U JPH0295940 U JP H0295940U
- Authority
- JP
- Japan
- Prior art keywords
- data
- output terminal
- digital
- outputs
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の第一の実施例の構成を示す
ブロツク図、第２図は同実施例の動作を説明する
ための波形図、第３図、第４図は各々従来のデイ
ジタル／アナログ変換回路の構成例を示すブロツ
ク図である。
１……データ処理回路、２……第１デイジタル
／アナログ変換器、３……第２デイジタル／アナ
ログ変換器、４……加算器。
FIG. 1 is a block diagram showing the configuration of the first embodiment of this invention, FIG. 2 is a waveform diagram for explaining the operation of the same embodiment, and FIGS. 3 and 4 are conventional digital/analog circuits, respectively. FIG. 2 is a block diagram showing an example of the configuration of a conversion circuit. 1... Data processing circuit, 2... First digital/analog converter, 3... Second digital/analog converter, 4... Adder.
Claims (1)
変換して出力するデイジタル／アナログ変換回路
において、 (b) フルスケールが共にＦＳである第１、第２
のデイジタル／アナログ変換器と、 (c) 前記入力デイジタルデータＸが予め設定さ
れているデータΔより大であるか、データ（−Δ
）より大でデータΔより小であるか、データ（−
Δ）より小であるかを判別し、 第１の場合には第１の出力端からＸを、第２の
出力端からデータＦＳを各々出力し、 第２の場合には、第１の出力端から、 （Ｘ／２）＋（Δ／２） を、第２の出力端から、 （Ｘ／２）＋（ＦＳ−Δ／２） を各々出力し、 第３の場合には、第１の出力端から０を、第２
の出力端から（Ｘ＋ＦＳ）を各々出力し、前記第
１の出力端のデータを前記第１のデイジタル／ア
ナログ変換器へ、また、前記第２の出力端のデー
タを前記第２のデイジタル／アナログ変換器へ各
々出力するデータ処理回路と、 (d) 前記第１、第２のデイジタル／アナログ変
換器の出力およびレベル（−ＦＳ）の信号を加算
する加算手段と、 を具備してなるデイジタル／アナログ変換回路
。[Claims for Utility Model Registration] (a) In a digital/analog conversion circuit that converts input digital data
(c) whether the input digital data X is greater than the preset data Δ or the data (−Δ
) is greater than data Δ, or data (−
Δ), and in the first case, outputs X from the first output terminal and outputs data FS from the second output terminal, and in the second case, outputs the data FS from the first output terminal. (X/2) + (Δ/2) is output from the second output terminal, and (X/2) + (FS-Δ/2) is output from the second output terminal, and in the third case, the first 0 from the output end of the second
outputs (X+FS) from the output terminals of each, the data at the first output terminal is sent to the first digital/analog converter, and the data at the second output terminal is sent to the second digital/analog converter. A digital/analog converter comprising: a data processing circuit that outputs data to each converter; and (d) adding means that adds the outputs of the first and second digital/analog converters and the level (-FS) signal. Analog conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP458389U JPH0295940U (en) | 1989-01-19 | 1989-01-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP458389U JPH0295940U (en) | 1989-01-19 | 1989-01-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0295940U true JPH0295940U (en) | 1990-07-31 |
Family
ID=31207227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP458389U Pending JPH0295940U (en) | 1989-01-19 | 1989-01-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0295940U (en) |
-
1989
- 1989-01-19 JP JP458389U patent/JPH0295940U/ja active Pending
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