JPS62127122U - - Google Patents
Info
- Publication number
- JPS62127122U JPS62127122U JP1488386U JP1488386U JPS62127122U JP S62127122 U JPS62127122 U JP S62127122U JP 1488386 U JP1488386 U JP 1488386U JP 1488386 U JP1488386 U JP 1488386U JP S62127122 U JPS62127122 U JP S62127122U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- output terminal
- terminal
- delay circuit
- analog switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Networks Using Active Elements (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図ａ〜ｄは、第１図に示す入出力信号のタイ
ムチヤート、第３図は従来の一例を示すブロツク
図である。
１……スイツチ、２……差動増幅器、３，３１
，３２，３Ｎ……単位時間遅延回路、４……バツ
フアアンプ、５……アナログスイツチ制御部、６
……アナログスイツチ。
FIG. 1 is a block diagram showing an embodiment of the present invention.
2A to 2D are time charts of the input/output signals shown in FIG. 1, and FIG. 3 is a block diagram showing an example of the conventional system. 1...Switch, 2...Differential amplifier, 3,31
, 32, 3N... unit time delay circuit, 4... buffer amplifier, 5... analog switch control section, 6
...Analog switch.
Claims (1)
とした差動増幅器と、入力端子を前記差動増幅器
の出力端子と接続した単位時間遅延回路と、入力
端子を前記単位時間遅延回路の出力端子と接続し
たバツフアアンプと、入力端子を前記バツフアア
ンプの出力端子と接続し、入力信号数をカウント
した後単位遅延時延時間だけオン信号を出力する
アナログスイツチ制御部と、入力端子を前記バツ
フアアンプの出力端子と接続し、制御端子を前記
アナログスイツチ制御部の出力端子と接続したア
ナログスイツチと、一方の接点を前記単位時間遅
延回路の出力端子と接続し、他方の接点を前記差
動増幅器のプラス入力端子と接続したスイツチと
を含むことを特徴とする遅延回路。 A differential amplifier with a negative input terminal as an input terminal of a signal to be delayed, a unit time delay circuit with an input terminal connected to an output terminal of the differential amplifier, and an input terminal connected with an output terminal of the unit time delay circuit. an analog switch control unit that connects an input terminal to an output terminal of the buffer amplifier and outputs an ON signal for a unit delay time after counting the number of input signals; and connects the input terminal to the output terminal of the buffer amplifier. and an analog switch whose control terminal is connected to the output terminal of the analog switch control section, one contact is connected to the output terminal of the unit time delay circuit, and the other contact is connected to the positive input terminal of the differential amplifier. A delay circuit comprising a switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1488386U JPH0540586Y2 (en) | 1986-02-03 | 1986-02-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1488386U JPH0540586Y2 (en) | 1986-02-03 | 1986-02-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62127122U true JPS62127122U (en) | 1987-08-12 |
| JPH0540586Y2 JPH0540586Y2 (en) | 1993-10-14 |
Family
ID=30805289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1488386U Expired - Lifetime JPH0540586Y2 (en) | 1986-02-03 | 1986-02-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0540586Y2 (en) |
-
1986
- 1986-02-03 JP JP1488386U patent/JPH0540586Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0540586Y2 (en) | 1993-10-14 |
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