JPS6277403U - - Google Patents

Info

Publication number
JPS6277403U
JPS6277403U JP16709785U JP16709785U JPS6277403U JP S6277403 U JPS6277403 U JP S6277403U JP 16709785 U JP16709785 U JP 16709785U JP 16709785 U JP16709785 U JP 16709785U JP S6277403 U JPS6277403 U JP S6277403U
Authority
JP
Japan
Prior art keywords
amplifier
recording
noise reduction
switching means
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16709785U
Other languages
Japanese (ja)
Other versions
JPH0531681Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985167097U priority Critical patent/JPH0531681Y2/ja
Publication of JPS6277403U publication Critical patent/JPS6277403U/ja
Application granted granted Critical
Publication of JPH0531681Y2 publication Critical patent/JPH0531681Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案回路の概略構成図、第2図は従
来回路の概略構成図である。 3…ノイズリダクシヨンアンプ、4…録音アン
プ、6,7…切換手段としてのスイツチ、8…グ
ラフイツクイコライザ回路。
FIG. 1 is a schematic diagram of a circuit according to the present invention, and FIG. 2 is a diagram of a conventional circuit. 3... Noise reduction amplifier, 4... Recording amplifier, 6, 7... Switch as switching means, 8... Graphic equalizer circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 録音入力信号をノイズリダクシヨンアンプを通
じて録音アンプに導く録音回路において、前記ノ
イズリダクシヨンアンプと録音アンプの間にグラ
フイツクイコライザ回路を接続する切換手段を設
け、該切換手段によりグラフイツクイコライザ回
路を接続すると同時に前記ノイズリダクシヨンア
ンプをフラツトアンプに切換えるようにしたこと
を特徴とする録音回路。
In a recording circuit that leads a recording input signal to a recording amplifier through a noise reduction amplifier, a switching means for connecting a graphic equalizer circuit is provided between the noise reduction amplifier and the recording amplifier, and the switching means connects the graphic equalizer circuit. At the same time, the noise reduction amplifier is switched to a flat amplifier.
JP1985167097U 1985-10-30 1985-10-30 Expired - Lifetime JPH0531681Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985167097U JPH0531681Y2 (en) 1985-10-30 1985-10-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985167097U JPH0531681Y2 (en) 1985-10-30 1985-10-30

Publications (2)

Publication Number Publication Date
JPS6277403U true JPS6277403U (en) 1987-05-18
JPH0531681Y2 JPH0531681Y2 (en) 1993-08-16

Family

ID=31098708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985167097U Expired - Lifetime JPH0531681Y2 (en) 1985-10-30 1985-10-30

Country Status (1)

Country Link
JP (1) JPH0531681Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5787323U (en) * 1980-11-18 1982-05-29
JPS58131413U (en) * 1982-02-27 1983-09-05 パイオニア株式会社 tape deck

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5787323U (en) * 1980-11-18 1982-05-29
JPS58131413U (en) * 1982-02-27 1983-09-05 パイオニア株式会社 tape deck

Also Published As

Publication number Publication date
JPH0531681Y2 (en) 1993-08-16

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