JPS61191617U - - Google Patents
Info
- Publication number
- JPS61191617U JPS61191617U JP7525485U JP7525485U JPS61191617U JP S61191617 U JPS61191617 U JP S61191617U JP 7525485 U JP7525485 U JP 7525485U JP 7525485 U JP7525485 U JP 7525485U JP S61191617 U JPS61191617 U JP S61191617U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- section
- timer circuit
- amplifier
- amplifier section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案の一実施例によるオーデイオア
ンプ装置のブロツク図であり、第２図は従来のタ
イマー回路のブロツク図である。
１……タイマー回路、２……リレースイツチ群
、３……タイマー回路からの制御信号、４……入
力電源、５……アンプ装置用電源、６……チユー
ナ装置用電源、７……録音デツキ用電源、８……
補助電源用、９……タイマー・スイツチ本体、４
１……タイマー回路、４２……リレースイツチ群
、４３……タイマー回路からの制御信号、４４…
…入力電源、４５……アンプ用電源、４６……チ
ユーナ装置用電源、４７……録音デツキ用電源、
４８……補助電源、４９……アンプ装置本体、５
０……アンプ部、５１……入力音源選択用制御信
号、５２……入力音源選択回路、５３……録音出
力選択用制御信号、５４……録音出力選択回路。
FIG. 1 is a block diagram of an audio amplifier device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional timer circuit. 1... Timer circuit, 2... Relay switch group, 3... Control signal from the timer circuit, 4... Input power supply, 5... Power supply for amplifier device, 6... Power supply for tuner device, 7... Recording deck. Power supply for 8...
For auxiliary power supply, 9...Timer switch body, 4
1... Timer circuit, 42... Relay switch group, 43... Control signal from the timer circuit, 44...
... Input power supply, 45 ... Power supply for amplifier, 46 ... Power supply for tuner device, 47 ... Power supply for recording deck,
48...Auxiliary power supply, 49...Amplifier device main body, 5
0... Amplifier section, 51... Control signal for input sound source selection, 52... Input sound source selection circuit, 53... Control signal for recording output selection, 54... Recording output selection circuit.
Claims (1)
立な装置として有し、前記アンプ部にタイマー回
路を内蔵することを特徴とするオーデイオ装置。 What is claimed is: 1. An audio device comprising a tuner section, a recording deck section, and an amplifier section as independent devices, the amplifier section having a built-in timer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7525485U JPS61191617U (en) | 1985-05-20 | 1985-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7525485U JPS61191617U (en) | 1985-05-20 | 1985-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61191617U true JPS61191617U (en) | 1986-11-28 |
Family
ID=30616302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7525485U Pending JPS61191617U (en) | 1985-05-20 | 1985-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61191617U (en) |
-
1985
- 1985-05-20 JP JP7525485U patent/JPS61191617U/ja active Pending