JPS62129819U - - Google Patents
Info
- Publication number
- JPS62129819U JPS62129819U JP1748786U JP1748786U JPS62129819U JP S62129819 U JPS62129819 U JP S62129819U JP 1748786 U JP1748786 U JP 1748786U JP 1748786 U JP1748786 U JP 1748786U JP S62129819 U JPS62129819 U JP S62129819U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- switch
- resistor
- input terminal
- cartridge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Amplifiers (AREA)
Description
第1図は本考案に係るイコライザー回路の一実
施例を示す回路図、第2図、第3図は従来のイコ
ライザー回路を示す回路例である。
Amp.1:MMカートリツジ用増幅回路、A
mp.2:MCカートリツジ用増幅回路、R1,
R2:抵抗、S11―a,S11―b:切換えス
イツチ。
FIG. 1 is a circuit diagram showing one embodiment of an equalizer circuit according to the present invention, and FIGS. 2 and 3 are circuit examples showing conventional equalizer circuits. Amp. 1: Amplifier circuit for MM cartridge, A
mp. 2: MC cartridge amplifier circuit, R1,
R2: Resistor, S11-a, S11-b: Changeover switch.
Claims (1)
カートリツジ用の第2の増幅回路と、前記第1の
増幅回路の入力端と前記第2の増幅回路の入力端
との間に接続された第1の抵抗と、前記第1の抵
抗に並列に接続された第1のスイツチと、前記第
2の増幅回路の入力端と接地間に接続された第2
の抵抗と、前記第1または第2の増幅回路のいず
れか一方の出力を選択する第2のスイツチとを有
し、前記第1のスイツチにより前記第1の抵抗を
短絡したとき、前記第2のスイツチにより前記第
2の増幅回路からの出力を選択することを特徴と
するイコライザー回路。 A first amplifier circuit for MM cartridge and MC
a second amplifier circuit for a cartridge; a first resistor connected between an input terminal of the first amplifier circuit and an input terminal of the second amplifier circuit; and a first resistor connected in parallel to the first resistor. a first switch connected to the switch, and a second switch connected between the input terminal of the second amplifier circuit and ground.
and a second switch that selects the output of either the first or second amplifier circuit, and when the first switch short-circuits the first resistor, the second An equalizer circuit characterized in that the output from the second amplifier circuit is selected by a switch.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1748786U JPS62129819U (en) | 1986-02-12 | 1986-02-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1748786U JPS62129819U (en) | 1986-02-12 | 1986-02-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62129819U true JPS62129819U (en) | 1987-08-17 |
Family
ID=30810292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1748786U Pending JPS62129819U (en) | 1986-02-12 | 1986-02-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62129819U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06249680A (en) * | 1993-02-23 | 1994-09-09 | Graphtec Corp | Input device for recording signal |
-
1986
- 1986-02-12 JP JP1748786U patent/JPS62129819U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06249680A (en) * | 1993-02-23 | 1994-09-09 | Graphtec Corp | Input device for recording signal |
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