JPS5967013U - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS5967013U
JPS5967013U JP16026482U JP16026482U JPS5967013U JP S5967013 U JPS5967013 U JP S5967013U JP 16026482 U JP16026482 U JP 16026482U JP 16026482 U JP16026482 U JP 16026482U JP S5967013 U JPS5967013 U JP S5967013U
Authority
JP
Japan
Prior art keywords
amplifier
muting circuit
phase input
negative phase
input part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16026482U
Other languages
Japanese (ja)
Inventor
通範 内藤
Original Assignee
株式会社ケンウッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ケンウッド filed Critical 株式会社ケンウッド
Priority to JP16026482U priority Critical patent/JPS5967013U/en
Publication of JPS5967013U publication Critical patent/JPS5967013U/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のミューティング回路を示すブロック図、
第2図は本考案に係るミューティング回路の実施側番示
すブロック図である。 1:増幅器、2:増幅器の出力部、3:増幅器の逆相入
力部、R1,R2:抵抗、Sl:第1のスイッチング回
L S2:第2のスイッチング回路。
Figure 1 is a block diagram showing a conventional muting circuit.
FIG. 2 is a block diagram showing the implementation side number of the muting circuit according to the present invention. 1: amplifier, 2: output section of amplifier, 3: anti-phase input section of amplifier, R1, R2: resistor, SL: first switching circuit L S2: second switching circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 増幅器の出力部と該増幅器の逆相入力部との間に直列的
に挿入された2つの抵抗器と、該抵抗器間をアースする
ための第1のスイッチング回路と、上記逆相入力部側に
接続されている抵抗器の両端を短絡するための第2のス
イッチング回路とを備え、上記第1、第2のスイッチン
グ回路を制御することにより上記増幅器のミューティン
グを行なわせるように構成されていることを特徴とする
ミューティング回路。
two resistors inserted in series between the output part of the amplifier and the negative phase input part of the amplifier, a first switching circuit for grounding between the resistors, and the negative phase input part side. a second switching circuit for short-circuiting both ends of a resistor connected to the amplifier, and is configured to mute the amplifier by controlling the first and second switching circuits. A muting circuit characterized by:
JP16026482U 1982-10-25 1982-10-25 Muting circuit Pending JPS5967013U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16026482U JPS5967013U (en) 1982-10-25 1982-10-25 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16026482U JPS5967013U (en) 1982-10-25 1982-10-25 Muting circuit

Publications (1)

Publication Number Publication Date
JPS5967013U true JPS5967013U (en) 1984-05-07

Family

ID=30352544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16026482U Pending JPS5967013U (en) 1982-10-25 1982-10-25 Muting circuit

Country Status (1)

Country Link
JP (1) JPS5967013U (en)

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