JPH0350245U

JPH0350245U -

Info

Publication number: JPH0350245U
Application number: JP10750489U
Authority: JP
Priority date: 1989-09-13
Filing date: 1989-09-13
Publication date: 1991-05-16

Description

[Brief explanation of the drawing]

第１図は本考案によるインストラクシヨンメモ
リシステムの一実施例を示すブロツク図、第２図
は第１図に示すＣＰＵの動作例を説明するための
模式図、第３図は同実施例の動作例を説明するた
めのタイミング図、第４図は本考案によるインス
トラクシヨンメモリシステムの他の実施例を示す
ブロツク図である。１……ＣＰＵ、３……インストラクシヨンメモ
リ部、４……アドレスバス、５……データバス、
６……インストラクシヨンバス、７……コントロ
ーラ、８……メインインストラクシヨンメモリ、
９……サブインストラクシヨンメモリ、１０……
セレクタ。 FIG. 1 is a block diagram showing an embodiment of the instruction memory system according to the present invention, FIG. 2 is a schematic diagram for explaining an example of the operation of the CPU shown in FIG. 1, and FIG. 3 is a block diagram of the same embodiment. FIG. 4 is a timing diagram for explaining an example of operation. FIG. 4 is a block diagram showing another embodiment of the instruction memory system according to the present invention. 1...CPU, 3...Instruction memory section, 4...Address bus, 5...Data bus,
6... Instruction bus, 7... Controller, 8... Main instruction memory,
9...Subinstruction memory, 10...
selector.

Claims

[Scope of utility model registration request]

address bus, instruction bus,
In an instruction memory system in which each part of a circuit and a CPU are connected via a data bus, there is a main instruction memory used as a main instruction memory, a sub-instruction memory used when jumping, and a main instruction memory used when jumping. A controller that decodes the jump instruction before the CPU and provides a jump destination address to the sub-instruction memory when the instruction output from the memory includes a jump instruction. instruction memory system.