JPS62156738A - Program controller - Google Patents

Abstract

PURPOSE:To increase a loop processing speed by applying an address to an instruction ROM through the 2nd program counter during a loop processing mode and then issuing a loop start address after the loop end address through the 1st program counter. CONSTITUTION:When a PCA 12 designates an address (N-1) of an instruction ROM 11, an instruction is read out to an instruction register 15 to start a loop and set K to a loop counter. A decoder 16 decodes this instruction to output the loop counter loading signal and set the loop frequency K to a loop counter 17, then sets a loop end address (N+3) to a loop address register 19. A comparator 20 outputs a coincidence signal when a PCB 13 is equal to (N+3). When the loading signal of the PCB 13 is set at 1, the contents of the PCB 13, the contents (N+1) are loaded to the PCB 13. In other words, the instruction of an address (N+1) is executed after the instruction of the address (N+3) and a loop having no overhead is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a program control device for repeatedly executing a series of computer instructions a preset number of times at high speed.

2. Description of the Related Art Conventionally, a program control device for performing a loop operation is constructed as shown in FIG. (1) is an instruction ROM that stores processor instructions; (2) is the instruction ROyt;
A program counter that gives the address of (L), (3)
is an instruction register that holds the contents of the program ROM (1), (4) is a decoder that decodes the contents of the instruction register (3) and provides control signals to each part of the processor, and (5) is a loop counter that executes a series of instructions. It consists of a down counter that counts the number of loops during repeated execution. (6) is a zero detection circuit that detects that the content of the loop counter (5) is zero, (7) is a knot circuit, and (8)
) is an AND circuit that provides a load signal for the program counter (2) and a decrement signal for the loop counter (5).

FIG. 5 is an instruction statement diagram showing an example of the address of the instruction ROM (1) in FIG. 4 and the contents of the instruction.

(N+'l) address in instruction ROM (1), (N+2)
Let us consider that an address arithmetic instruction is repeatedly executed (N+1) times. At this time, address N contains an instruction (S
L C: Set Loop Counter instruction) is written, and at address (N+3), an instruction to end the loop and its operand, the loop start address (N+1)
is written. Figure 6 is a time chart of each part of the fourth unit, where A is the output of the program counter (2), B is the address of the instruction held in the instruction register (3), C is the address of the instruction executed by the processor, and D is the content of the loop counter (5), E is the SLC instruction decode signal and is a loop counter load signal that loads the loop counter (5) help number from the instruction register (3), and F is the AND circuit (8). )
The load signal from the instruction register (3) to the program counter (2) and the loop counter (5)
, and G is a decode signal of the loop end instruction.

When the program counter (2) specifies the N address of the instruction ROM (1), the instruction at the N address “Set Loop Counter (SLC: Set Loop Counter)” is executed.
r) The J instruction is read into the instruction register (3). The decoder (4) decodes this, issues a loop counter load signal as shown in FIG. 6(E), and sets the specified number of loops "K" from the instruction register (3) in the loop counter (5). Normally, the program counter (2) is incremented sequentially, and (N+1) and (N+2) of the instruction ROM (1) are incremented in order.
) The contents of the address "operation 1" and "operation 2" instructions are read into the instruction register (3), and the processor performs the operation under the control of the decoder (4). Next, the program counter (
When 2) accesses the (N+3) address of the instruction ROM (1), the "loop end" instruction at the (N+3) address is read into the instruction register (3), decoded by the decoder (4), and shown in Figure 3 (G). ) The decoded signal is output as shown below.

The zero detection circuit (6) outputs "1" to the NOT circuit (7) when the loop counter (5) is "zero", and outputs "0" when it is not "zero". When the loop counter (5) is not "0" when the "loop end" command is decoded, the output of the AND circuit (8) becomes "1" as shown in Figure 6 (F). The counter (2) is loaded with the specified loop start address (N+1) in the instruction register (3), and the loop counter (
5) is decremented. "End loop" like this
In this instruction, the loop counter (5) is decremented unless the contents of the loop counter (5) is "0", and at the same time, the program counter (2) is loaded with the loop start address (N+1) specified by the operand of this instruction, and the loop ends. It is formed. When the value of the loop counter (5) becomes "0", the output of the zero detection circuit (6) becomes "1", and in the "loop end" command, the output of the not circuit (7) becomes rO
J, and the output of the AND circuit (8) also becomes "0", so
No looping occurs. At this point, the loop is terminated, the loop is exited, and the next instruction at address (N+4) is executed.

The loop operation is performed when the value of the loop counter (5) changes from “K” to “
This continues until it reaches "0", so (N+1) address and (N+
2) The instruction at address is executed (N+1) times.

Problems to be Solved by the Invention In such a conventional configuration, the control for performing the loop is (N+
3) It is performed only after the decoder (4) finishes decoding the "loop end" command at the address. For this reason, an overhead of one machine cycle is generated until the program counter (2) is returned to and the address (W+1) is loaded, resulting in a problem that high-speed processing cannot be achieved when loop execution of calculations is performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a program control device that can eliminate overhead cycles occurring in each loop and execute loop processing of operations at high speed.

Means for Solving the Problems The program control device of the present invention controls the operation of a microprocessor by a microprogram stored in an instruction memory, and includes first and second program counters that provide addresses to the instruction memory. , a selection device for selecting which of the first and second program counters to give to the instruction memory; a register for holding a loop end address; and the contents of the register and the address to be given to the instruction memory. A comparator that detects a match and a loop counter that counts the number of loops are installed.
In the loop start command, the content of the first program counter selected by the selection device is loaded into a second program counter to switch the selection device, and when the comparison contents in the comparator match, the first program counter is loaded into the second program counter. The present invention is characterized in that the contents of the counter are loaded into the second program counter the number of times set in the loop counter.

Effect: According to this configuration, there are two program counters, a first and a second program counter, and during loop processing, the second program counter gives an address to the instruction ROM, and the first program counter holds the loop start address. However, after the loop end address, the loop start address is given from the first program counter to the second program counter.

Embodiment One embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 shows a block diagram of a program control device of the present invention.

(1■) is an instruction ROM that stores processor instructions, (
12) and (13) are first program counters (hereinafter referred to as PCA) that give the addresses of instructions R and OM (11), respectively.
) and a second program counter (hereinafter referred to as ).

PCB), (14) is PCB (12) and p
a multiplexer (15) that selects one of the outputs of CB (13) and outputs it to the instruction ROM (11);
An instruction register holds the contents read from the instruction ROM (11), and a decoder (16) decodes the contents of the instruction register (15) and provides control signals to each part of the processor.

(17) is a down counter that counts the number of loops when a series of instructions is repeatedly executed. (18) is the loop counter (17)
A zero detection circuit that detects that the content of is zero, (19
) is the loop address register (LAR) that holds the end address of the loop.
ster), (20) is the loop address register (19
) and the address given to the instruction ROM (11). (22) is a multiplexer (14).
), outputs select signals of PCA (12) and P CB (13), and outputs select signals of PCA (12) and P CB (13) to
CB (13) is a T flip-flop that controls the count up, (22) is a NOT circuit, (23) is an AND circuit that outputs a decrement signal for the loop counter (17), and (24) is a decode signal for the SLC instruction. Load signal to loop counter (17) and AND circuit (23)
), (25) is a PCA
(12) PCB AND circuit that gives a load signal from (13), (26) is PCB (13) PCA
This is an AND circuit that provides a load signal from (12).

FIG. 2 is an example of an instruction statement diagram showing the address of the instruction ROM (11) of FIG. 1 and the contents of the instruction. In Figure 2, (N
Let us consider that arithmetic instructions at addresses +1), (N+2), and (N+3) are repeatedly executed (K+1) times. At this time, the address (N-1) is a loop start command that specifies the set loop number jgK'', and the loop end address (N+3) is written at address N as its second operand.

Figure 3 is a time chart of each part in Figure 1 when the instruction in Figure 2 is executed, where A is the output of PCA (12) and B is the output of PCA (12).
Output of B (13), C is the address of the instruction held in the instruction register (15), D is the address of the instruction executed by the processor, E is the content of the loop counter (17), F is the loop address register (19) contents, G is the decoder (16)
The output is the load signal of the loop counter (17), and H is the output of the decoder (16), which is the loop address register (19).
), I is the positive output Q of the T flip-flop (21), J is the output of the AND circuit (25), and PCA (1
The load signal from P CB (13) in 2) is the output of the AND circuit (26) and the PCA (
12), L is the match signal of the comparator (20).

Next, the configuration shown in FIG. 1 will be explained in detail based on the operation.

The multiplexer (14) is a T flip-flop (21
) outputs the contents of PCA (12) when the positive output Q is "0", and outputs the contents of P CB (13) when Q is "1". Further, PCA (12) is counted up only when the negative output of the T flip-flop (21) is "1", and P CB (13) is counted up only when the positive output Q is "1".

Now, if the content of the T flip-flop (21) is rOJ, the positive output Q is "0" and the negative output τ is "1", and the multiplexer (14) selects and outputs the content of PCA (12). , P CB (13) are not counted up, but only PCA (12) is counted up.

That is, at this time, the instruction ROM (11) is PCA (
12) is used to give the address. PCA
When (12) specifies address (N-1) of instruction ROM (11), the instruction at address (N-1) "Start loop and set K to loop counter" is read into the instruction register (15).

The decoder (16) decodes this and outputs the loop counter load signal as shown in FIG.
17) Set the number of loops “K II”.Usually, the PC
A (12) is incremented, and when PCA (12) specifies address N, the loop end address (N+3), which is one of the operands of the loop start instruction, is set to the instruction register (
15). The decoder (16) is
) to output the LAR load signal and load the LAR (19)
Set the loop end address (N+3) to .

Also, at the rising edge of the loop counter load signal G, T
The contents of the flip-flop (21) are inverted so that the Q output becomes "1" and the -ζ- becomes "0", which means that from now on, the address of the instruction ROM (11) will be given by PCB (13). means. At the same time, this loop counter load signal G causes the PCB load signal, which is the output of the AND gate (26), to become "1" through the OR gate (24) as shown in FIG. 3(K). This signal causes P
The contents of PCA (12) (N+1 at this point) are loaded as the contents of CB (13).

In this way, in the loop start instruction, the loop count gt K jj is set in the loop counter (17), and the loop end address (N+
3) Set the two program counters PcA, PC
The program counter to be used is changed by loading the contents (N+1) of the previously used program counter PCA (12) of B into the other program counter P CB (13). Therefore, from now on, the address of instruction ROM (11) is P CB (13)
The content of PCB (12) stores the start address (N+1) of the loop. Instruction ROM (11
) The instruction “operation 1” stored at address (N+1) is P
CB (13) and is accessed by the instruction register (
15), the processor performs calculations under the control of the decoder (16). (N+2) address and (N+
3) The instructions "operation 2" and "operation 3" at the address are executed in the same way.

When P CB (13) becomes (N+3), instruction R
The address of OM (11) and the contents of LA R (19) match, and the comparator (20) outputs a match signal as shown in FIG. 3(L). The loop counter at this time (17
) is “K tp”, the output of the zero detection circuit (18) is “0”, and the output of the not circuit (22) is “1”.
”. Therefore, the output of the AND circuit (23) is “1
”. By this signal, the loop counter (17) is decremented and the value becomes (K-1), and the load signal of the PCB (13), which is the output of the AND gate (26), is transmitted through the OR circuit (24) as shown in FIG. ), this signal becomes “1” as shown in P CB (13)
The contents (N+1) of PCA (12) are loaded. In other words, the instruction at address (N+3) is followed by (N+1)
The instruction at the address is executed, forming a loop with no overhead.

In this way, the instruction ROM given by P CB (13)
If the address of (11) matches the contents of L A R (19) and the loop counter (17) is not zero, the loop counter (17) is decremented until it becomes "zero".

At the same time, the loop start address (N+1) stored in PCA (12) is loaded into P CB (13) to form a loop. When the loop counter (17) is "zero", the output of the zero detection circuit (18) is "1". At this time, the contents of P CB (13) are (
Even if P CB (13) becomes (N+3) and matches L A R (19), the loop operation is not performed, and P CB (13) becomes (N+4) and escapes from the loop. The loop counter (17) is “
The loop operation continues from “K” to “0”.
Because it is performed twice, "Operation 1", "Operation 2", and "Operation 3" are (
K+1) times.

After exiting this loop, if there is another loop start instruction, PCA (12) and PCB (
The role of 13) is reversed.

As described above, without performing a loop operation after decoding a useless instruction such as a "loop end instruction", the program counter will point to the loop start address after the loop end address, resulting in overhead during loop operation. Since there are no cycles, it is possible to speed up loop processing.

DETAILED DESCRIPTION OF THE INVENTION As described above, the program control device of the present invention has a first
, a second program counter and a selection device for selecting the contents of one of the first and second program counters and providing an address to the instruction memory, the contents loop of the first program counter being selected by the selection device; The start instruction loads the second program counter and switches the selection device so that the first program counter stores the start address of the loop. When the contents of the second program counter reach the loop end address, the loop start address stored in the first program counter is loaded and the loop operation is executed a predetermined number of times. Therefore, a loop end command is issued at the end of the loop. The overhead cycle for each loop in some conventional devices is removed, and the loop processing of calculations can be executed at high speed, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the program control device of the present invention, FIG. 2 is an instruction text diagram showing an example of the address of the instruction ROM in FIG. 1 and its instruction contents, and FIG. A time chart diagram of each part, Figure 4 is a block diagram of a conventional program control device, and Figure 5 is an instruction ROM in Figure 4.
FIG. 6 is a time chart of each part of FIG. 4. (11)...Instruction ROM, (12)...First program counter, (13)...Second program counter, (14)...Multiplexer [selection device], (
17)...Loop counter, (19)...Loop address register [register]. (20)... Comparator, (21)... T flip-flop agent Yoshihiro Morimoto Figure 2
-Figure 4

Claims (1)

[Claims] 1. First and second program counters that control the operation of the microprocessor by a microprogram stored in the instruction memory and provide an address to the instruction memory; a selection device for selecting whether to give contents to the instruction memory; a register for holding a loop end address; a comparator for detecting a match between the contents of the register and the address given to the instruction memory; and a comparator for counting the number of loops. A loop counter is provided, and when the contents of the first program counter selected by the selection device in the loop start command are loaded into the second program counter and the selection device is switched, and the comparison contents in the comparator match. A program control device configured to load the contents of a first program counter into a second program counter the number of times set in the loop counter.