JPS61187044A - Information processor - Google Patents

Information processor

Info

Publication number
JPS61187044A
JPS61187044A JP2760185A JP2760185A JPS61187044A JP S61187044 A JPS61187044 A JP S61187044A JP 2760185 A JP2760185 A JP 2760185A JP 2760185 A JP2760185 A JP 2760185A JP S61187044 A JPS61187044 A JP S61187044A
Authority
JP
Japan
Prior art keywords
arithmetic
mask
instruction
register
exception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2760185A
Other languages
Japanese (ja)
Other versions
JPH0417530B2 (en
Inventor
Hideo Hayashi
英男 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2760185A priority Critical patent/JPS61187044A/en
Publication of JPS61187044A publication Critical patent/JPS61187044A/en
Publication of JPH0417530B2 publication Critical patent/JPH0417530B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To make it unnecessary to wait the end of execution of an arithmetic unit before execution of an arithmetic exception mask change instruction, by providing a register where arithmetic exception mask information is held in accordance with the arithmetic unit from which an arithmetic exception may be reported. CONSTITUTION:A control circuit 2 decodes the instruction word in an instruction register 1 and instructs an arithmetic unit 8 to execute it if it is the instruction to be executed by the unit 8. At this time, contents of a register 3 where arithmetic exception mask information is held are taken into a mask register 5 corresponding to the arithmetic unit 8. If arithmetic exceptions are reported from arithmetic units 8-10, interrupt request signal generating circuits 11-13 compares them with contents of mask registers 5-7 corresponding to individual arithmetic units and generate and send interrupt request signals due to occurrence of arithmetic exceptions to the control circuit 2. In case of the arithmetic exception mask change instruction, contents of a mask register 3 and loaded data are compared with each other by a mask comparator; and if they coincide with each other, the following instruction is executed without waiting the end of execution of each arithmetic unit.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、命令実行制御に改良を施した情報処理装置に
関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device with improved instruction execution control.

(従来の技術) 従来、この種の情報処理装置においては演算例外発生時
、割込処理を行なうか否かを制御する演算例外マスク情
報を格納するレジスタは情報処理装置に1個有するのが
一般的であった。
(Prior Art) Conventionally, in this type of information processing device, it is common for the information processing device to have one register for storing operation exception mask information that controls whether or not to perform interrupt processing when an operation exception occurs. It was a target.

(発明が解決しようとする問題点) そのため、演算例外マスク情報を変更する命令を実行す
る際にはそれ以前に命令実行指示を送出した演算命令の
実行が完了し演算例外の報告タイミングを経過するまで
待つ必要があるという欠点があった。また、このとき演
算例外マスク情報を格納するレジスタの内容と新しく格
納するiスフ情報が同じ場合であっても上記と同様待つ
必要があった。
(Problem to be Solved by the Invention) Therefore, when executing an instruction to change the operation exception mask information, the execution of the operation instruction that previously sent the instruction execution instruction is completed and the timing for reporting the operation exception has passed. The drawback was that you had to wait until Further, at this time, even if the contents of the register storing the operation exception mask information and the newly stored i-space information are the same, it is necessary to wait in the same way as described above.

本発明の目的は、演算例外マスク情報を変更する命令を
実行する際、それ以前に命令実行指示を送出した演算命
令の実行の終了を待つことのないようにすることによυ
性能の向上を図ることができる情報処理装置を提供する
ことにある。
An object of the present invention is to avoid waiting for the completion of execution of the arithmetic instruction that previously issued an instruction execution instruction when executing an instruction that changes arithmetic exception mask information.
An object of the present invention is to provide an information processing device that can improve performance.

(問題点を解決するための手段) 前記目的を達成するために本発明−よる情報処理装置は
、演算例外発生時、演算例外マスク情報により、割込処
理を実行するか否かを判断する情報処理装置において、
演算例外マスク情報を格納する第1のマスクレジスタと
、演算例外を発生する複数の演算ユニットと、前記演算
ユニットに対する命令実行指示時、その演算ユニット対
応に前記第1のマスクレジスタの内容を格納する第2の
マスクレジスタと、前記演算ユニットからの演算例外発
生報告時、前記jg2のレジスタの内容により割込処理
要求を送出する前記演算ユニット対応毎の割込要求信号
生成回路と、前記第1のマスクレジスタの内容を変更す
る命令の実行時、前記第1のマスクレジスタのもとの内
容と新しく第1のマスクレジスタに格納した内容を比較
する比較器と、命令実行指示を出し、前記比較器出力を
受けたとき、その出力結果により後続命令の実行を演算
ユニットの演算実行終了を待たずに進めるか、待って進
めるかの制御をする制御回路とを有し・て構成されてい
る。
(Means for Solving the Problem) In order to achieve the above object, an information processing apparatus according to the present invention provides information for determining whether or not to execute interrupt processing based on operation exception mask information when an operation exception occurs. In the processing device,
a first mask register for storing arithmetic exception mask information; a plurality of arithmetic units that generate an arithmetic exception; and when an instruction execution instruction is given to the arithmetic unit, the contents of the first mask register are stored corresponding to the arithmetic unit; a second mask register; an interrupt request signal generation circuit for each of the arithmetic units that sends an interrupt processing request based on the contents of the jg2 register when the arithmetic unit reports the occurrence of an arithmetic exception; a comparator that compares the original content of the first mask register with the new content stored in the first mask register when executing an instruction that changes the contents of the mask register; When receiving the output, the control circuit controls whether to proceed with the execution of the subsequent instruction without waiting for the completion of the execution of the arithmetic unit or after waiting, depending on the output result.

(実施例) 次に本発明について図面を参照して説明する。(Example) Next, the present invention will be explained with reference to the drawings.

第1図は、本発明による情報処理装置の一実施例を示す
ブロック図である。命令レジスタ1は処理装置で実行す
べき命令語を保持するものである。
FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. The instruction register 1 holds instructions to be executed by the processing device.

制御回路2は命令を解読し命令実行指示を行ったシ、割
込処理要求にしたがって割込処理を行ったシする。マス
クレジスタ3は演算例外マスク情報を保持するレジスタ
である。演算ユニット8,9および10は演算命令の演
算を実行する回路であシ、各演算ユニットは通常それぞ
れ異なる種類の演算を実行する。例えば、8は固定小数
点演算ユニット、9は浮動小数点演算ユニットという具
合である。制御回路2が命令レジスタ1内の命令語を解
読し、例えば演算ユニット8で実行すべき命令であると
判断すると演算ユニット8に実行指示を与える。この実
行指示時、演算ユニット8に対応スるマスクレジスタ5
にマスクレジスタ3の内容を取り込む。すなわち、各演
算ユニットに対し実行指示を与えるとき演算ユニットに
対応するマスクレジスタにマスクレジスタ3の内容を取
り込む。割込要求信号生成回路11.12.13は各演
算ユニット8.9.IQよシ演算例外報告があ−)り際
、各演算ユニット対応のマスクレジスタ5゜6または7
と比較され演算例外発生による割込要求信号を生成する
。この割込要求信号は図示しない信号線により制御回路
2に送られる。命令レジスタ1に格納された命令が演算
例外のマスク変更命令である場合、制御回路2はマスク
レジスタ3に対しデータをロードする指示を与える。こ
のとき、マスクレジスタ3に格納されていた内容とロー
ドするデータをマスク比較器4で比較し、その結果は制
御回路2に与えられる。制御回路2は比較器4での比較
の結果が異っていることを示している場合、演算例外マ
スク変更命令の後続命令の実行は各演算ユニットの実行
が終了するまで待たせる。逆に異っていない、即ち同じ
場合には各演算ユニットの実行終了を待つことなく後続
命令の実行を行なう。
The control circuit 2 decodes the command, issues an instruction to execute the command, and performs interrupt processing in accordance with an interrupt processing request. Mask register 3 is a register that holds operation exception mask information. The arithmetic units 8, 9, and 10 are circuits that execute arithmetic operations based on arithmetic instructions, and each arithmetic unit usually executes a different type of operation. For example, 8 is a fixed point arithmetic unit, and 9 is a floating point arithmetic unit. When the control circuit 2 decodes the instruction word in the instruction register 1 and determines that it is an instruction to be executed by the arithmetic unit 8, for example, it gives an execution instruction to the arithmetic unit 8. At the time of this execution instruction, the mask register 5 corresponding to the arithmetic unit 8
The contents of mask register 3 are taken in. That is, when giving an execution instruction to each arithmetic unit, the contents of the mask register 3 are taken into the mask register corresponding to the arithmetic unit. The interrupt request signal generation circuit 11.12.13 is connected to each calculation unit 8.9. When an operation exception report is received due to IQ, the mask register 5゜6 or 7 corresponding to each operation unit is
It is compared with , and an interrupt request signal is generated due to the occurrence of an arithmetic exception. This interrupt request signal is sent to the control circuit 2 via a signal line (not shown). If the instruction stored in the instruction register 1 is a mask change instruction for an operation exception, the control circuit 2 instructs the mask register 3 to load data. At this time, the mask comparator 4 compares the contents stored in the mask register 3 with the data to be loaded, and the result is given to the control circuit 2. When the comparison result in the comparator 4 indicates that the control circuit 2 is different, the control circuit 2 causes the execution of the instruction subsequent to the arithmetic exception mask change instruction to wait until the execution of each arithmetic unit is completed. Conversely, if they are not different, that is, they are the same, the subsequent instructions are executed without waiting for the completion of execution of each arithmetic unit.

(発明の効果) 以上、説明したように本発明は演算例外報告を行なう可
能性のある演算ユニット対応に演算例外マスク情報を保
持するレジスタをもつことにより演算例外マスク変更命
令の実行前に演算ユニットの実行終了を待つ必要がない
こと、および演算例外マスク変更命令の実行前と後でマ
スクレジスタの内容に変更がない場合、演算ユニットの
実行終了を待つ必要がないことにより性能の向上が図れ
るという効果がある。
(Effects of the Invention) As described above, the present invention provides registers that hold calculation exception mask information for calculation units that may perform calculation exception reporting, so that the calculation unit It is said that performance can be improved because there is no need to wait for the execution of the arithmetic unit to finish, and if there is no change in the contents of the mask register before and after execution of the arithmetic exception mask change instruction, there is no need to wait for the execution of the arithmetic unit to finish. effective.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による情報処理装置の一実施例を示すブ
ロック図である。 1・・Φ命令レジスタ 2・・・制御回路 3・・・演算例外マスク 4・・・マスク比較器 5〜7・・番演算ユニット対応マスクレジスタ8〜10
・・・演算ユニット
FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. 1... Φ instruction register 2... Control circuit 3... Arithmetic exception mask 4... Mask comparators 5-7... Arithmetic unit corresponding mask registers 8-10
...Arithmetic unit

Claims (1)

【特許請求の範囲】[Claims] 演算例外発生時、演算例外マスク情報により、割込処理
を実行するか否かを判断する情報処理装置において、演
算例外マスク情報を格納する第1のマスクレジスタと、
演算例外を発生する複数の演算ユニットと、前記演算ユ
ニットに対する命令実行指示時、その演算ユニット対応
に前記第1のマスクレジスタの内容を格納する第2のマ
スクレジスタと、前記演算ユニットからの演算例外発生
報告時、前記第2のレジスタの内容により割込処理要求
を送出する前記演算ユニット対応毎の割込要求信号生成
回路と、前記第1のマスクレジスタの内容を変更する命
令の実行時、前記第1のマスクレジスタのもとの内容と
新しく第1のマスクレジスタに格納した内容を比較する
比較器と、命令実行指示を出し、前記比較器出力を受け
たとき、その出力結果により後続命令の実行を演算ユニ
ットの演算実行終了を待たずに進めるか待つて進めるか
の制御をする制御回路とを有することを特徴とする情報
処理装置。
In an information processing device that determines whether or not to execute an interrupt process based on operation exception mask information when an operation exception occurs, a first mask register that stores operation exception mask information;
a plurality of arithmetic units that generate an arithmetic exception; a second mask register that stores the contents of the first mask register corresponding to the arithmetic unit when an instruction execution instruction is given to the arithmetic unit; and an arithmetic exception from the arithmetic unit. When reporting an occurrence, the interrupt request signal generation circuit for each of the arithmetic units sends an interrupt processing request according to the contents of the second register, and when executing an instruction to change the contents of the first mask register, the A comparator that compares the original content of the first mask register with the new content stored in the first mask register; An information processing device comprising: a control circuit that controls whether execution is to proceed without waiting for the completion of execution of an arithmetic operation by an arithmetic unit or to proceed after waiting.
JP2760185A 1985-02-15 1985-02-15 Information processor Granted JPS61187044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2760185A JPS61187044A (en) 1985-02-15 1985-02-15 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2760185A JPS61187044A (en) 1985-02-15 1985-02-15 Information processor

Publications (2)

Publication Number Publication Date
JPS61187044A true JPS61187044A (en) 1986-08-20
JPH0417530B2 JPH0417530B2 (en) 1992-03-26

Family

ID=12225441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2760185A Granted JPS61187044A (en) 1985-02-15 1985-02-15 Information processor

Country Status (1)

Country Link
JP (1) JPS61187044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05224931A (en) * 1991-09-06 1993-09-03 Internatl Business Mach Corp <Ibm> Method and system for representing program condition in execution and for notifying condition with signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05224931A (en) * 1991-09-06 1993-09-03 Internatl Business Mach Corp <Ibm> Method and system for representing program condition in execution and for notifying condition with signal

Also Published As

Publication number Publication date
JPH0417530B2 (en) 1992-03-26

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