JPH0293756A - Parallel processing computer - Google Patents

Abstract

PURPOSE:To easily obtain synchronization between computers even when computation is not repeated by sending end information through a contact means to the other computer for the computer to parallelly execute the computation when processing is finished in the self-computer. CONSTITUTION:The value of a mask signal register 44i is set by an input line 491. However, when the processed result of a central processing unit 10i is needed, for the contents of the register, the contents are caused to be 1 for the register 44i and to be 0 for the other register. When an execution ending signal 50i is inputted from the unit 10i to correspond to the register, for which the 1 is set out of the outputs of the register 41i, an AND circuit 41i turns on the output and sets 1 through an OR circuit 42i to a correspondent ending signal register 43i. When the output of the register 43i and the output of the register 44i are completely coincident, necessary processing is wholly finished. Such a condition is detected by a coincidence circuit 470 and a coincidence output line 480 is turned on. Thus, the pertinent unit 10i executes the processing in the unit itself.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel processing computer suitable for high-speed processing.

[Conventional technology]

Parallel processing is a method of performing high-speed calculations by sharing and executing calculation processing among a plurality of processing devices. There are various types of conventional parallel processing computers, but as shown in Japanese Patent Application Laid-Open No. 62-187971, the main ones are those that execute repetitive calculations such as the D○ loop of the Fortran program in parallel. Ta.

[Problem to be solved by the invention]

The above conventional technology does not take into account parallel processing of parts not included in repetitive calculations, such as Do loops,
These were processed sequentially. For example, the calculations (1) A=B+C (2) n=(B+10)*C (3) E=A+D were performed sequentially. However, even in such operations, (1) and (2) can be executed in parallel. However, 3) needs to be executed after variables A and D are determined by the calculations in (1) and (2), so (1) and (2)
When executed in parallel by different processing devices, the processing device executing (3) needs to know that they have both finished, and this problem is called "synchronization." During repeated calculations, the same formula is executed by multiple processing units for cases where only the value on the right side differs, so the processing time is almost the same and it is easy to synchronize, but in the example above, the Processing times may vary, and conventional techniques have not been able to achieve general synchronization at high speed.

An object of the present invention is to provide a parallel processing computer that can quickly synchronize parallel processing even in areas other than repetitive calculations and perform high-speed processing.

[Means to solve the problem]

The purpose of the above is to provide a means of communication from each computer to other computers to notify them of the completion of execution of the assigned calculation, and to receive a report from each computer of the completion of execution so that the calculation required by the computer has already been completed. This is achieved by providing a determination means for each computer that determines whether the

[Effect]

Computers executing calculations in parallel send a completion report to other computers via communication means when the processing on one computer is completed. The computer waiting for this parallel processing to finish is
Since you are given information on which computer's processing should have been completed along with the calculation formula you want to execute, you can check the completion report from each computer using the determination means and determine whether all necessary calculations have been completed. Synchronous processing of parallel processing can be performed at high speed.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the entire embodiment of a computer according to the present invention, and includes central processing units (CPUs) 101 to 10.
4, Bus 2oO, May V-Re 300, Execution end communication line 5
00, and the central processing units 101-104 are provided with end determination circuits 401-404, respectively. Although the number of central processing units is four, any number may be used.

FIG. 2 shows the configuration of the end determination circuit 401 (others have the same configuration), including AND circuits 411 to 414, an OR circuit 42,
1 to 424, end signal registers 431 to 434. It consists of mask signal registers 441-444° and a matching circuit 470.

The values of the mask signal registers 441 to 444 are input to the input line 49.
It is set by 1, but its contents are.

When the processing results of the central processing unit 10i (i=1 to 4) are required, the register 44i (j=1 to 4) is set to "1",
The others are set to "0". AND circuits 411-41
4 is the central processing unit 1 corresponding to the mask signal register output 451 to 454 whose output is '1'.
When the execution end signals 501 to 504 from 01 to 104 are input, the output is turned on, and 11 is sent to the corresponding end signal register 431 to 434 via OR circuits 421 to 424.
Set 111. Output 4 of registers 431-434
61 to 464 and the outputs 451 to 454 of the mask signal registers 441 to 444 completely match, when all necessary processing has been completed, this is detected by the minus number circuit 470, and the match output line 480 is turned on. becomes. As a result, the corresponding central processing unit 101 performs processing within itself. When the processing is completed, the input line 490 causes the registers 441 to
The contents of 444 are reset.

In the above embodiment, the operation of this embodiment will be explained using the program shown in FIG. 3 as an example. Assuming that the main program 610 is executed by the central processing unit 101, set-mesh-
By executing the queue #2 instruction, programs 620 and 630 that can operate in parallel are activated as follows. FIG. 4 shows the processing flow of the set-mesh-queue command. In step 700, set-
It is checked whether it is possible to allocate as many central processing units as the number of operands of the mesh-queue instruction (2 in this case), and if possible, the process moves to step 710.

Here, the mask signal registers 441 to 444 corresponding to the assigned central processing unit are set to II 1.
Set #. In this case central processing unit 102.10
3 is assigned, each of the mask signal registers 441 to 444 of the central processing unit 101 has "0" and "
1'', "1", and '0' are set. Subsequently, in step 720, the allocated central processing units are activated, and thereby programs 620 and 630 are executed in each of central processing units 102 and 103. When these executions are completed, the central processing bag [102, 103 is set
-Execute the end command. Figure 5 shows this set -en
d instruction, and the corresponding execution end signal 50i (i
=1 to 4) to the contact [500. In this case, the end signal 50 is generated when the processing of the central processing units 102 and 103 is completed.
2.503 is sent. Then central processing bag @10
In the end determination circuit 401 of No. 1, the end signal register 4
32 and 433 are set to 1'', and 1111+ is output to the output 480 of the minus number circuit 470.

On the other hand, in the central processing unit 101, set -mesh
-queue # Processing after 2 instructions is performed, and t
Assume that the processing has progressed to the est-reset command. te
The processing contents of the st-reset command are shown in FIG.

In step 900, it is checked whether the coincidence output line 480 is on, and if it is on, the end signal registers 431 to 434 are reset in step 910 in preparation for the next process. At step 900, if match output line 480 is not on, then
Wait until the processing of programs 620 and 630 is completed.

When the completion of the processing of the programs 620 and 630 is confirmed in this way, the processing of the instructions after the test-set instruction is continued in the central processing unit 101, but the synchronization of this parallel processing is not achieved by the hardware. Therefore, the processing time for synchronization is short and the high speed of parallel processing can be fully demonstrated.

〔Effect of the invention〕

According to the present invention, synchronization between computers can be easily and quickly achieved even when calculations are not repeated, so that high-speed parallel processing can be easily realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the entire embodiment of the present invention, FIG. 2 is a diagram showing the configuration of an end determination circuit, FIG. 3 is an example of a program executed in the embodiment of FIG. 1, and FIG. 6 to 6 are diagrams showing the processing contents of the command shown in FIG. 3. 101-104...Central processing unit, 401-404.
・End determination circuit 1.411 to 414...AND circuit, 4
21-424...OR circuit, 431-434...end signal register, 441-444...mask signal register, 470...-number circuit, 500...execution end communication line.

Claims (1)

[Scope of Claims] 1. A plurality of central processing units, communication means for sending an end signal to other central processing units when processing in each central processing unit is completed, and communication means specified in advance within the own central processing unit. A determination means corresponding to each central processing unit is provided to determine whether or not the end signal has been sent from the central processing unit via the communication means, and the central processing unit that executes the main program is capable of parallel processing. When executing multiple processes, the process is assigned to a vacant central processing unit and execution is started, and at the same time, the assigned central processing unit is designated as the specified central processing unit in the determination means within the own device. By storing it in , and then executing the end judgment instruction,
The parallel processing computer is characterized in that the parallel processing computer is configured to execute an instruction following the termination determination instruction when the determination means detects that the termination signal is generated from all of the specified central processing units. 2. The determining means has bits corresponding to each central processing unit, and only the bits corresponding to the designated central processing unit are “
a first register to which "1" is set; gate means for detecting when the end signal is sent from the designated central processing unit using the set value of the first register; A second register stores and holds the end signal detected by the gate means, and the contents of the first and second registers are compared, and when they match, the end signal is sent from all of the designated central processing units. 2. A parallel processing computer according to claim 1, further comprising comparison means for outputting a signal indicating that the parallel processing has been sent.3. 2. The parallel processing computer according to claim 1, wherein the parallel processing computer executes an instruction for issuing a termination signal at the end of the assigned processing and sends the termination signal to the communication means.