JPS61292749A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To decrease the transmission times of memory requests with a pipeline information processor by detecting the overlap degree of two operands and making good use of the data obtained by a single memory request. CONSTITUTION:When the overlap of both operands, for example, as shown by the diagrams is recognized by a comparator 3 and an overlap detecting circuit 4, it is reported to an address production control part 5 that both operands should be supplied only to non-overlap parts 25 and 26. Therefore the part 5 gives an indication to an address calculating part to produce the address following an address a2 and starts the supply of operands with said address. While an arithmetic control part 6 stores the offset value to an operand register 8a and an operand 25 to an operand register 8b respectively. Then an arithmetic executing part 9 performs successively the operations.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic processing device in a pipelined information processing device that creates operands for arithmetic instructions using operands obtained through multiple memory accesses. .

〔overview〕

The present invention detects the duplication state of two operands in an arithmetic processing unit in a pipelined information processing device that creates operands for an arithmetic instruction using operands obtained through multiple memory accesses, and performs operations for the same address. By providing a means to effectively create operands for arithmetic instructions without repeating memory accesses, the number of memory requests sent is reduced and instruction execution time is reduced.

[Conventional technology]

Conventionally, in an instruction that performs an operation using two operands obtained through multiple memory accesses, the instruction operates to obtain the two operands in sequence without checking the degree of overlap between the two operands, and uses the obtained operands. I have been performing calculations.

[Problem that the invention seeks to solve]

In the arithmetic processing device using the conventional instruction execution method described above, if the operand addresses overlap, two memory requests are sent to the same address, which has the disadvantage that the instruction execution time increases. .

An object of the present invention is to provide an arithmetic processing device that reduces instruction execution time and improves performance by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The arithmetic processing device of the present invention is an arithmetic processing device of a pipelined information processing device that creates an operand of an arithmetic instruction using an operand obtained by multiple memory accesses, and the arithmetic processing device of the present invention is an arithmetic processing device of a pipelined information processing device that creates operands of an arithmetic instruction using operands obtained through multiple memory accesses. The present invention is characterized by comprising means for holding the operands, means for detecting the degree of overlap between the two operands, and control means for instructing a change in the calculation method of the supplied operands based on the detection result of the degree of overlap.

[For production]

In the arithmetic processing device of the present invention, the holding means holds the start and end addresses of two operands obtained by memory access, the detecting means detects the degree of overlap between these two operands, and if overlap is detected, The instruction execution time can be reduced by controlling the control means to execute an operation using the operand obtained from one memory request without sending two memory requests to the same address. .

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the address generation unit 1, the generated start and end addresses of the first and second operands are sent to the address register (A) via the signal line 11.

B, Cs D) Sequentially stored in 2a, 2b, 2c s 2d. This address register (A, BSC, D)
The operand addresses stored in 2a, 2b, 2c, and 2d are compared in the comparison circuit 3, and the output is reported to the duplication detection circuit 4 via signal lines 12, 13, 14, and 15. The duplication detection circuit 4 examines the positional relationship between both operands, determines in what order memory access should be performed and the operands are supplied to the arithmetic unit, and sends this output via the signal line 16 to the address generation control unit. 5
It also reports to the arithmetic control unit 6 via the signal line 17.
will be reported.

The address generation unit 1 executes address calculation according to the recognized memory access order, and the operands obtained by this memory access are sequentially stored in the operand buffer 7 via the signal line 18. operand buffer 7
The operands stored in are read out to the operand registers (J, , K) 8a, 8b according to instructions from the arithmetic control unit 6. At this time, operand register (JSK) 8a
, 8b are arbitrarily specified according to the instruction from the calculation control unit 6 according to the calculation order. In this way, the operand to be operated on is the operand add starter (J, K) 8a.

8b, predetermined calculations are performed in the calculation execution unit 9, and the calculation results are fed back to the calculation control unit 6 via the signal line 19, and it is determined whether or not to continue the execution.

Based on the above determination, the arithmetic control unit 6 repeatedly instructs the continuation of the arithmetic operation, or notifies the result of this instruction and the end of this instruction to the address generation unit 1, prompting the start of the next instruction.

The feature of the present invention is that in FIG.
A, B, C, D) 2a, 2b, 2c, 2d.

This is because a comparison circuit 3, a redundancy detection circuit 4, and an arithmetic control section 6 are provided.

Hereinafter, a specific example of the operation of this embodiment will be explained using an explanatory diagram showing the positional relationship of two operands to be calculated as shown in FIGS. 2(a) and 2(b).

FIG. 2(a) shows a case where two operands partially overlap. In this case, the start address a1 and end address a2 of the fourth operand of the first operand, and the start address bl and end address b2 of the second operand are the address registers (A, B, C, , D) 2a.

2b, 2c, and 2d. When the comparator circuit 3 and the duplication detection circuit 4 recognize the case shown in FIG. 2(a) in which both operands partially overlap, each operand is supplied once, and
It is determined that accesses are to be made in the order of 22, 23, 24, 25, and 26, and this result is reported to the address generation control section 5 and the calculation control section 6 via signal lines 16.17.

Based on this report, the address generation control unit 5 increments the order from the first operand start address calculation until the second operand end address calculation, and performs address calculations so as to perform memory access once each. In addition,
For operand access using start address a1, address calculation is performed when operand duplication is detected, so performing memory access at this point will further improve performance. Perform access.

This device uses a pipeline system, so operand 2
When 1 is supplied to the arithmetic unit via the signal line 18, the arithmetic control unit 6 instructs to store it in the operand register J8a, and when the next operand 22 is also supplied to the arithmetic unit, the operand register 8b is stored. Instruct to store. The two operands stored in the operand registers J8a and J8b are operated on by the arithmetic execution unit 9 based on instructions from the arithmetic control unit 6. At this time, the next operand 23 is stored in the operand buffer 7, and
The calculation execution results are reported to the calculation control section 6 via the signal line 19. When the instruction is not completed, the operation control unit 6 sends an instruction to take in the operand 23 stored in the operand buffer 7 to the operand register J8a. In this way, based on instructions from the calculation control unit 6, the order operand registers (J, K) 8a, 8b are updated and calculations are performed.

When the arithmetic execution unit 9 identifies the end of the computation or the arithmetic control unit 6 identifies the end of the instruction, the arithmetic control unit 6 notifies the address generation control unit 5 of the end of the instruction and urges the address generation control unit 5 to start the next instruction.

Figure 2 (bl is a case where the two operand start addresses match but the end addresses are different; in this case, as in the case of various duplications described above, addresses a1, a2, bl
, b2 are address registers (A, BSC, D), respectively.
2a, 2b, 2c, 2d, and the comparison circuit 3
When the duplication detection circuit 4 recognizes that the duplication of both operands is the case shown in FIG. The report is sent via the signal line 16. Upon receiving this report, the address generation control unit 5
An instruction is given to the address calculation section to generate a netast address for address a2, and operand supply using this address is started. Further, when the arithmetic control section 6 receives this report via the signal line 17, it stores the offset value in the operand register J8a, stores the operand 25 in the operand register 8b, and stores the offset value in the operand register J8b.
Execute the calculation. The calculation results are reported to the calculation control section 6 via the signal line 19. When the instruction is not completed, the next operand 26 is read from the operand buffer 7, 8b is updated in the operand register, and the same operation as above is performed.

〔Effect of the invention〕

As explained above, the present invention checks the duplication state of two operands, and if there is a duplicate operand, the memory can be obtained by one memory request without sending two memory requests to the same address. By effectively using the data stored in the memory, the number of times memory requests are sent can be reduced, the instruction execution time can be shortened, and performance can be improved.

4. Detailed description of the invention FIG. 1 is a block diagram of an embodiment of the present invention.

FIGS. 2(a) and 2(b) are explanatory diagrams showing the positional relationship between two operands to be calculated.

1...Address generation unit, 2a, 2b, 2c, 2d...
・Address register ASBSC, D, 3... Comparison circuit, 4... Duplication detection circuit, 5... Address generation control section, 6... Arithmetic control section, 7... Operand buffer,
8a, 8b...operand registers J, K, 9...
Arithmetic execution unit, 11-19...Signal line, 21-26...
・Operand, al, bl...Start address, a2,
b2... Terminal address.

Claims (1)

[Claims] (1) In an arithmetic processing unit in a pipelined information processing device that creates operands for an arithmetic instruction using operands obtained through multiple memory accesses, means for holding the start and end addresses of the two operands; means for detecting the degree of overlap between the two operands; means for controlling the necessity of the memory access according to the result of detecting the degree of overlap; and means for controlling the operation method of the supplied operands according to the result of detecting the degree of overlap. An arithmetic processing device comprising a control means for giving instructions.