JPH0243628A - Information processor - Google Patents

Abstract

PURPOSE:To efficiently send an operand request and to execute the high speed by comparing the degenerated value of the lower-order bit of respective addresses. CONSTITUTION:The processor has an overlapping detecting means 7 composed of a means to identify that the instruction to need to detect the overlapping of two operands is obtained and to instruct the overlapping detection, a comparator 50 of a high-order n-m-1 bit of respective addresses for the operand in which the operand length defined by the instruction is defined by a binary (m) bit, a means to degenerate the information of the low-order m+1 bit of respective addresses and a means to compare respective degenerated values. Since the operand length is 2<m>, the high-order (n)-(m+1) bit of the address is compared, and at the time of non-coincidence, difference >=2<m+1> of both addresses is obtained and overlapping is not executed. When the high-order n-(m+1) bit of the address is coincident, the presence and absence of the overlapping are decided considering the conditions of the low order (m+1) bit. Thus, due to the overlapping detection, the operand supply does not stop and the performance does not reduce.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and more particularly to a method for detecting duplication of operands in operand supply in a preceding control unit.

[Conventional technology]

Conventionally, this type of duplication detection has been carried out by determining the duplication of operands by examining the positional relationship between the two operand start addresses and the end address obtained by adding the operand lengths. The two operands (at, a2) can be specified arbitrarily, but if the lengths 2 are the same length, compare the difference between the start addresses of the two operands (lal-a21) and the operand length 2, and find that 1al-a21< J! In this case, it was judged as a duplicate. Also, two operands (al.

If the length of a2) can be specified arbitrarily, the positional relationship between the end addresses at, al+421 of the source operand and the destination start address a2 is a1≦a2≦a.
l+j! In the case of 1, it was determined to be a duplicate.

(Problems to be Solved by the Invention) The conventional operand duplication detection method described above is accurate, but because it uses an address adder to find the difference or the end address of the operands, it is difficult to supply operands for duplication detection. The disadvantage is that it stops and performance deteriorates.

[Means for Solving the Problems] An information processing device of the present invention includes means for performing n-bit address calculation and holding the output, and identifying that an instruction requires detecting duplication of two operands. means for instructing duplicate detection, and for an operand whose operand length is defined by m binary bits,
-1 bit comparator, means for degenerating the lower m+1 bits of information of each address, and means for comparing each degenerated value with the duplication detection means.

[Operation] Since the land length is 2", first the upper n of the address
-(m+1) bits are compared, and if they do not match, the difference between both addresses is 2 m+1, and there is no overlap. If the upper n-(m+1) bits of the address match, the lower n-(m+1) bits of the address match.
) The presence or absence of duplication is determined taking into account the conditions of the bits.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an information processing apparatus according to the present invention.

The selection circuits 1, 2.3 switch the input information of the address adder 4. The switching instruction is sent to the control block 5 via the signal line 30.
instructions from. The input information to the selection circuits 1, 2 and 3 is the information necessary to calculate the operand start address specified by the command words base, index, and displacement via the signal lines 21, 22, and 23, and the signal line 2.
This information is necessary to obtain the subsequent address of the previously calculated address selected by 4°25.27. The output 26 of the address adder 4 is sent to an address conversion section and an address holding section (none of which are shown), and also to a register 6 and a duplication detection block 7. Register 6 is controlled from control block 5 by signal line 31.

The output of the register 6 is output to the duplication detection block 7 and the selection circuit 1 via a signal line 27. The control block 5 determines whether or not to perform operand duplication detection based on the command information supplied via the signal line 20, and determines whether or not to use the comparison result signal 28 of the duplication detection block 7 as valid information. Further, when it is determined that there is a duplication based on the operand duplication result, the result is reported to the arithmetic unit (not shown) through the signal line 32, and the operand supply of the instruction is transferred to the arithmetic unit, and the address adder 4 is used. stop.

Generally, when an instruction enters the instruction decoding stage, the instruction is decoded, and when the signal line 20 instructs the instruction and control block 5, which is a general instruction and does not require operand duplication detection and does not require continuous operand supply, the instruction is decoded. The line 30 causes the selection circuits 1, 2.3 to select the signal lines 21, 22, and 23, respectively, and inputs them to the address adder 4. The addition result is sent to the address converter via the signal line 26, and the operation ends. In the next cycle, the operation is repeated according to the information of the next instruction. Further, in the case of a one-operand type in which operand duplication detection is unnecessary but continuous operand supply is performed, the information is transmitted to the control block 5 via the signal line 20, and the signal line 30 is connected to the selection circuits 1, 2, . 3, the signal lines 21, 22, and 23 are selected, and the address added in the address adder 4 is sent to the address conversion unit via the signal line 26, and the signal line 31
According to the instruction from the control block 5, the output of the signal line 26 is taken into the register 6. In the next cycle, control block 5
are the outputs of register 6, signal line 27 and signal line 24
．． 25 is selected by the selection circuit 1.2.3 by the signal line 30, and the result added by the address adder 4 is sent to the signal line 2.
6 as in the previous cycle. After sending out the necessary number of requests, the control block 5 receives information on the next command via the signal line 2o and operates. A two-operand type instruction sends the output of the address adder 26 to the address holding section, and selects the starting address in the address holding section from the selection circuit 1.
, 2.3 operates in the same manner as the one-operand type instruction described above, except for selection in steps 2.3.

The operation of instructions that require operand duplication detection will be explained.

When the command information is transmitted to the control block 5 via the signal line 20, the control signal 30 is sent to the selection circuit 1.2.3 via the signal line 21.2 to determine the first operand starting address a1.
2. Select 23 and input it into address adder 4.

The output of the adder 4 is sent to the address conversion section/address holding section via the signal line 26, and in the 0th cycle, which is held in the register 6 under the control of the signal line 31, the output is sent to the second operand start address a2. In order to find the signal line 21°22.23,
Enter the address into address adder 4. The output of the adder 4 is sent to the address conversion section/address holding section via the signal line 26 and is also input to the duplication detection block 7. On the other hand, the operand start address a1 held in register 6
is input to the duplication detection block 7 via the signal line 27.
In the duplication detection block 7, operand start addresses a1 and 82 are used to test whether there is any duplication.

FIG. 2 is a block diagram showing the duplication detection block 7. As shown in FIG. The data on the signal lines 26 and 27 are all n-bit addresses, and when detecting 0 duplications represented by An to Ao and Bn to B0, the start addresses of both operands are farther apart than the maximum operand length defined by the instruction. In order to confirm this, we will explain the operation when the maximum operand length is 16 bytes in the instruction definition (n=28.m=4), for example, at an operand start byte address defined by 28 bits. The upper 23 bits (A1.~As, Bat~BS) of the signal lines 26.27 are input to the comparator 5o via the signal line 40.41, and the comparison result is input to the detection circuit 51 via the signal line 46. . The lower four bits (A3 to Ao, Bs to BO) are each logically summed and input to the detection circuit 51 via signal lines 44 and 45.

Bit A4. B4 is input to the detection circuit 51 via signal lines 42 and 43. The detection circuit 51 considers the next state to be a duplicate, and in this example assumes a transfer command.

Let the values of the signal lines 27 and 26 be A and B, respectively. When the signal line 46="0", IA-Bl≧32, and there is no overlap. When the signal line 46="1" and the signal lines 42 and 43 are both "0" and "1", IA-Bl≦15,
There is overlap.

Signal line 46="1", signal line 42="0", signal line 43
= ``1'', signal line 44.45 = ``0'', then B-A =
16, and there are no duplicates. Signal line 46-“1”, signal A
142="0", signal line 43="1", signal line 44;"
0", when signal line 45="1", B-A=16+α
(1≦α≦15), and again there is no overlap. signal line 4
6="1", signal line 42="0", signal line 43="l"
, when the signal line 44="1" and the signal line 45="0", B
-A≦15, and there is overlap. Signal @4B="1",
Signal @42="0", signal @43="1", signal line 44
．． 45="1", if the value of the lower 4 bits B, ~B0 is equal to or larger than the value of the lower 4 bits A3~80, there is no overlap, but conversely, the value of the lower 4 bits A, ~Ao is the lower There is an overlap when the value is greater than the value of 4 bits B3-B0. In this case, it is assumed that there is overlap, signal line 46 = "1", signal line 4
2 When the signal line 43 is “0”, the signal line 46 is “1”
The magnitude relationship of A and B is opposite to that in the case where the signal line 42 is "O" and the signal line 43 is "1".

The signal line 28 is turned on when there is overlap. In control block 5, it is recognized as an operand duplication instruction, so signal line 2
When the level of 8 during the cycle is reported as 0 overlap, which is considered valid, the control block 5 stops operating in the next cycle to stop supplying the operands, and sends the signal @32 to the arithmetic unit.
The information is transmitted via. By reporting to the arithmetic unit, the operation of this instruction in the advance control unit is completed, and the execution is left to the arithmetic unit. Upon completion in the arithmetic unit, the operation of this block resumes. On the other hand, if it is determined that there is no overlap, the control block 5 performs control to input the operand start addresses at and a2, which were previously sent to the address holding unit, into the address adder 4 as base addresses, and only the required number of operands are input to the address adder 4. Have the supply implemented.

〔Effect of the invention〕

As explained above, the present invention detects operand duplication using a simple operand duplication means, and although the number of cases in which it is determined to be duplication increases, it eliminates the need for machine cycles spent on duplication checks, and continuously performs necessary operand duplication. Speed is increased by sending operand requests without waste, and since an adder separate from the address adder is not required as a duplicate detection means, the amount of hardware can be reduced, which is a significant effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the information processing apparatus of the present invention, and FIG. 2 is a block diagram of the duplication detection block 7 in FIG. 1. 1 to 3... Selection circuit, 4... Address adder 5... Control block, 50... Comparator, 51... ...Detection circuit, 40-46...Signal line.

Claims (1)

[Scope of Claims] 1. In an information processing device capable of instructing read/write of operands in a preceding control unit, means for calculating an n-bit address and holding the output; means for identifying an instruction that needs to be detected and instructing duplicate detection;
An information processing device comprising: a comparator for comparing -1 bits, a means for degenerating lower m+1 bits of information of each address, and a duplication detection means comprising a means for comparing each degenerated value.