JPS62296236A - Interruption processor for microprocessor - Google Patents

Abstract

PURPOSE:To attain the parallel processing of a usual processing and an interruption processing by providing a program storing means, first and second instruction selecting means, a timing generator, a CPU control means and an interrupt control means. CONSTITUTION:The first and second programmable counters 600 and 700 select a special instruction stored into a program ROM 100 based on the output of a timing generator 500. A CPU control circuit 800 controls the action of a processor based on the output of the timing generator 500 and the instruction sent from the program ROM 100. An interrupting control circuit 900 receives an interrupting request signal impressed to an interrupt signal input terminal 20, and selects and executes the usual program and the interruption processing program stored into the program ROM 100 to the first programmable counter 600 and the second programmable counter 700 by the time division respectively.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to an interrupt processing device for a microprocessor, which enables parallel processing of normal processing and interrupt processing.

2. Description of the Related Art In recent years, von Neumann microprocessors have been widely used in various fields, and they consist of a program storage means for storing a program consisting of a group of instructions to be executed sequentially, and a data storage means for reading and writing digital data. a data bus connecting the input/output terminals of the data storage means and the input/output terminals of the calculation means; a control means for controlling the operations of the data storage means and the arithmetic means; a timing generator for generating an instruction execution timing signal; and a specific instruction stored in the program storage means based on the output of the timing generator. It is characterized by having a command selection means.

Further, a typical configuration thereof is shown in Japanese Patent Publication No. 58-33584 (hereinafter abbreviated as Document 1).

Problems to be Solved by the Invention Around 7, the Neumann microprocessor shown in Document 1 processes data in a predetermined order, so as the program becomes enormous, The problem is that the cycle of asynchronously manually importing external data and processing data based on it becomes long. Interrupts are often used to solve such problems, but in conventional interrupt processing methods, when an interrupt request signal is received, normal processing is interrupted and interrupt processing is started. There is a problem in that normal processing stops until the interrupt processing program is finished. For example, if serial data with an identification signal (uniform number) unique to each processor is sent from a master processor to a large number of slave processors via a common 1ffi (3), each slave processor In order to decide whether or not the data is the content that it should receive, it is necessary to execute the reception routine by interrupt processing for the entire 1υ1 period when the serial data is sent from the master processor, and during that period, the normal program is not executed. This completely stops, and each slave processor placed in such an environment is essentially only able to receive serial data.

Means for Solving the Problems In order to solve the above-mentioned problems, the microprocessor interrupt processing system of the present invention includes a program storage means for storing a program consisting of a group of instructions to be executed sequentially;
first and second instruction selection means for selecting a specific instruction stored in the program storage means; a timing generator for generating an instruction execution timing signal; and controlling the operation of the processor based on the output of the timing generator. a CPU control means for receiving an interrupt request signal, and time-sharingly selecting a normal program and an interrupt processing program stored in the program storage means to the first instruction selection means and the second instruction selection means, respectively; It is equipped with an interrupt control means for at least execution.

According to the present invention, with the above-described configuration, it is possible to obtain a microprocessor that enables parallel processing of normal processing and interrupt processing.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of a microprocessor according to an embodiment of the present invention, and includes a program ROM 100 in which a program consisting of a group of instructions to be executed sequentially is stored.
and data memory for reading and writing digital data.
(Indicated by the abbreviation RAM in the figure.)2
00, an I10 port 250 that shares the data memory 200, the first address decoder 210, and the second address decoder 220, and an arithmetic unit (indicated by the abbreviation ALU in the figure) that executes arithmetic and logical operations on digital data. (hereinafter abbreviated as ALU)3
00, a first register 310 and a second register 320 that store the calculation results of the LtJ300, a common input/output terminal of the data memory 200 and the I10 port 250, and an input/output terminal of the ALU300. A timing generator (in the figure, T
It is indicated by the abbreviation G. ) 500, and a first programmable counter (indicated by the abbreviation PCI in the figure) 600 that selects a specific instruction stored in the program ROM 100 based on the output of the timing generator 500. , a second programmable counter (indicated by the abbreviation PO2 in the figure) 700, and the timing generator 5.
A CPU control circuit 800 that controls the operation of the processor based on the output of 00 and instructions sent from the program ROM 100 receives interrupt request No. 48 applied to the interrupt signal input terminal 20, and executes the program R.
A normal program and an interrupt processing program stored in the OM 100 are transferred to the first programmable counter 600 and the second programmable counter 70, respectively.
Interrupt control if to select and execute at hour υl at 0
f! 1 circuit 900, and a control bus 450 that supplies control signals from the CPtJ control circuit 800 and the interrupt control circuit 900 to each block.

Regarding the microprocessor configured as above,
The operation will be explained with reference to the configuration diagram shown in FIG. 1 and the timing chart of the main parts shown in FIG.

First, FIGS. 2A and 2B show the timing signal waveform output from the timing generator 500 based on the clock signal waveform supplied to the external clock input terminal 10 of FIG. 2 shows the interrupt request signal waveform applied to the interrupt signal input terminal 20, and the second diagram shows the shave mode generation signal waveform generated inside the interrupt control circuit 900.
2F shows the waveform of the Kuntrol signal sent from the υj entry control t1 circuit 900 to the control bus 450. In addition, FIG. 2G shows the CPU control circuit 800.
In the waveform diagram, the cycles marked with an N symbol are normal processing cycles, and the cycles marked with a ■ symbol are interrupt processing cycles.

Now, in the timing chart of FIG. 2, time t1
Previously, the first programmable counter 600 and the CPU control circuit 800 selected instructions stored in the program ROM 100 and executed them sequentially, but when an interrupt request signal was applied to the interrupt input terminal 20 at time t1, , the interrupt control circuit 900 initiates an interrupt processing mode and maintains this state for a period until executing a return instruction at time [2]. As can be seen from Figure 2G,
In the interrupt processing mode from time tl to time L2, when the signal waveform of the second [pE is at the active level, that is, the "l" level, the first programmable counter 600, first address decoder 210, and first register When the operation of 310 is enabled and the normal processing that has been executed up to that point is intermittently executed, and the signal waveform of FIG. Decoder 220
, the operation of the second register 320 is enabled and the interrupt processing program is executed.

In this way, in the microprocessor shown in Figure 1, when an interrupt request signal is generated, the normal program that was being executed up to that point and the interrupt processing program are executed alternately in a time-sharing manner. Regular programs will not stop completely during this period, making it possible to build a system with higher real-time performance.

Furthermore, Fig. 3 shows the second waveform obtained from the signal waveforms in Fig. 2B and Fig. 2C.
Fig. 2 is a circuit wiring diagram showing a specific example of an interrupt control circuit 900 for generating signal waveforms E and F, and the signal waveforms shown in Fig. 2C and H are applied to input terminals 20 and 30, respectively. , when a signal waveform generated by a return command is applied to the input terminal 40, the output terminal 50,
From 60.70, the signal waveforms of the second diagram, E, and F are obtained, respectively.

By the way, in the embodiment shown in FIG. 1, the program ROM 100 and data memory 200 are provided separately, but they can also be allocated to the same memory space, similar to a microprocessor with a conventional interrupt processing mechanism. , the first programmable counter 600
Alternatively, it is also possible to save the second programmable counter 700 in the form of a register to a stack area in the data memory, or to similarly save either the first register 310 or the second register 320 to the stack area. In addition, in the embodiment, parallel processing is enabled by time-sharing switching between normal processing and interrupt processing every machine cycle when transitioning to interrupt processing mode, but the micro ROM is provided. In processors or processors that perform pipeline processing, it may be more convenient to switch at macro instruction breakpoints, or just before a conditional branch instruction, rather than switching every machine cycle.

Effects of the Invention As is clear from the above description, the microprocessor of the present invention has a program storage means (program I?0M10) that stores a program consisting of a group of instructions to be executed sequentially.
0), first and second instruction selection means (first programmable counter 600 and second programmable counter 700) that select a specific instruction stored in the program storage means, and an instruction execution timing signal. A timing generator 500 that generates the generated timing, and a CPU control means (CPU system?ffn circuit 800) that controls the operation of the processor based on the output of the timing generator.
and receiving an interrupt request signal, the normal program and the interrupt processing program stored in the program storage means are transferred to the first instruction selection means and the second instruction selection means, respectively.
The instruction 'J:A' is characterized by being equipped with 11 interrupt control means (interrupt control circuit 900) that causes the A-save means to select and execute the command in a time-sharing manner, thereby enabling parallel processing of normal processing and interrupt processing. It is possible to obtain a microprocessor that does

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention, FIG. 2 is a timing chart of the main parts of FIG. 1, and FIG. 3 is a circuit connection diagram showing a specific example of an interrupt control circuit. 100...Program ROM, 200...
...Data memory, 300...Arithmetic unit, 400
...Data bus, 500...Timing generator, 600...First programmable counter, 700...Second programmable counter, 800...・CPU control circuit, 90
0...Interrupt control circuit. Name of agent: Patent attorney Toshio Nakao
(I: ccIU Q date - φ

Claims (4)

[Claims] (1) A program storage means for storing a program consisting of a group of instructions to be executed sequentially, first and second instruction selection means for selecting a specific instruction stored in the program storage means, and an instruction execution timing signal a timing generator that generates a timing generator, a CPU control means that controls the operation of the processor based on the output of the timing generator, and a CPU control means that receives an interrupt request output and executes a normal program and an interrupt processing program stored in the program storage means, respectively. An interrupt processing device for a microprocessor, comprising interrupt control means for causing the first instruction selection means and the second instruction selection means to select and execute the commands in a time-sharing manner. (2) A program ROM that stores a program consisting of a group of instructions to be executed sequentially, first and second programmable counters that select specific instructions stored in the program ROM, and generates an instruction execution timing signal. a timing generator; and a CP that controls the operation of the processor based on the output of the timing generator.
A U control circuit receives an interrupt request output, and causes the first programmable counter and the second programmable counter to select and execute a normal program and an interrupt processing program stored in the program ROM in a time-sharing manner, respectively. The microprocessor interrupt processing device according to claim 1, further comprising an interrupt control circuit. (3) A program storage means for storing a program consisting of a group of instructions to be executed sequentially, first and second instruction selection means for selecting a specific instruction stored in the program storage means, and a means for reading and writing digital data. first and second address selection means for selecting a specific address of said data storage means; arithmetic means for performing arithmetic operations on digital data; and first and second address selection means for storing arithmetic results. a data bus that connects the input/output terminals of the data storage means and the input/output terminals of the calculation means, a timing generator that generates an instruction execution timing signal, and a processor operation based on the output of the timing generator. a CPU control means that receives an interrupt request signal and time-shares a normal program and an interrupt processing program stored in the program storage means to the first instruction selection means and the second instruction selection means, respectively. 1. An interrupt processing device for a microprocessor, comprising interrupt control means for selecting and executing an address and switching the first and second address selection means and the first and second registers, respectively. (4) A program ROM that stores a program consisting of a group of instructions to be executed sequentially, first and second programmable counters that select specific instructions stored in the program ROM, and generates an instruction execution timing signal. a timing generator; and a CP that controls the operation of the processor based on the output of the timing generator.
A U control circuit receives an interrupt request signal and causes the first programmable counter and the second programmable counter to select and execute a normal program and an interrupt processing program stored in the program ROM in a time-sharing manner, respectively. 3. The microprocessor interrupt processing device according to claim 3, further comprising an interrupt control circuit.