JPH01185738A - Address trace circuit - Google Patents

Abstract

PURPOSE:To effectively collect address trace information by common hardware for a processor whose instruction set is differently by detecting the generation of branch by comparing an address just before execution with a value on which 1 is added on the address. CONSTITUTION:An adder 14 adds 1 on an instruction address 30 under execution held at a first instruction address holding register 11, and the signal 13 is sent to a second instruction address holding register 20. Meanwhile, a third instruction address holding register 16 holds the instruction address 30 which is held at the first instruction address holding register 11 and executed just before holding time. Therefore, the contents of the first and second instruction address holding registers 11 and 20 are equal when no branch is performed, and they go to different values when the branch is performed. Then, a comparator 15 compares the content of the instruction address holding register 11 with that of the register 20, and sends the result to a stack control circuit 24. In such a way, it is possible to obtain address information with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and more particularly to an address trace circuit that stores a series of executed instruction addresses.

[Conventional technology]

The recent development of microcomputers is remarkable, and the development of application systems for them is also active. The development of efficient programs in a short period of time is currently an important issue, and further progress is expected in various development tools including address tracers in terms of cost and efficiency.

Conventionally, this type of address trace circuit has the following two types.
types are known. The first one is configured to store all the addresses of the executed series of instructions. On the other hand, the second one is configured to detect the occurrence of a branch instruction, that is, means for determining a branch instruction, means for determining the occurrence of an interrupt, and means for storing the addresses of instructions before and after the branch. have.

[Problem to be solved by the invention]

However, these conventional address trace circuits have the following drawbacks.

In the former case, it is necessary to store all the addresses of the most recent multiple steps of a series of executed instructions. Therefore, if the storage of steps required for analysis of execution results is also taken into consideration, there is a drawback that the hardware l becomes large.

In the latter case, there are no drawbacks like the former, but it is necessary to consider a control circuit for detecting the occurrence of a branch, etc.
The disadvantage was that the circuit became complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address trace circuit that can obtain address information with a simple configuration by comparing the addresses of executed instructions and detecting the occurrence of a branch.

[Means to solve the problem]

The address trace circuit of the present invention is a circuit that is provided in a central processing unit and stores the addresses of a series of executed instructions.
an instruction address holding circuit; an adder circuit that adds 1 to the content held in the first holding circuit; and a second adder circuit that sets a value obtained by adding 1 to the address of the instruction immediately before execution, which is the addition result by the adder circuit. an instruction address holding circuit; a third instruction address holding circuit that sets the instruction address immediately before execution held in the first instruction address holding circuit; and a third instruction address holding circuit that sets the instruction address immediately before execution held in the first and second instruction address holding circuits; A comparison circuit compares the address of the instruction with the value obtained by adding 1 to the address of the instruction immediately before execution, and when the comparison result by this comparison circuit does not match, the contents of the first and third instruction address holding circuits are The device is equipped with a stack for storing a plurality of words and a stack control circuit.

Therefore, when the address trace circuit according to the present invention is used, the address of the instruction immediately before execution is compared with the value obtained by adding 1 to the address of the instruction immediately before execution, so the occurrence of a branch can be easily detected. . Furthermore, address trace information can be collected using common and simple hardware even for instructions from different processors.

〔Example〕

The present invention will be described in detail below with reference to Examples.

FIG. 1 is a block diagram showing an embodiment of an address trace circuit according to the present invention, and FIG. 2 is a timing diagram showing operations when execution of an instruction branches.

In FIG. 1, a first instruction address holding register 11 receives an instruction address from a central processing unit (not shown) via a signal line 12. Further, via the signal line 13, the received instruction address is sent to the adder 14 and the comparator 15.
, the third instruction address holding register 16, and the stack memory 17. The +1 adder 14 sends the instruction address to the second instruction/address register 20 via the signal line 19. The output from the second instruction address register 20 is input to the comparator 15 via the signal line 22. The output of the comparator 15 is sent to the stack control circuit 24 via the signal line 23, and the stack '5i control circuit 24 stores the output in the stack memory 26 via the signal 0 line 25.

Next, the operation will be explained.

An instruction address 28 (FIG. 2a) is sent to the first instruction address holding register 11 from a central processing unit (not shown).

The first instruction address holding register 11 is a one-word register that holds the instruction address 29 (b in the figure) that is being executed. This instruction address 29 (b in the figure) being executed is sent to the +1 adder 14, the comparator 15, and the third instruction address holding register 16. The adder 14 has the first
The address of the currently executed instruction held in the instruction address holding register 11, that is, the instruction address 30 that was executed immediately before.
Add 1 to (Fig. 2 d). A signal 31 (second
C) is sent to the second instruction address holding register 20. This second instruction address holding register 20 is a 1-word register that predicts and holds the instruction address to be executed when there is no branch, based on the value of the signal 31 which is the value of the signal 31 that is obtained by adding 1 to the instruction address executed immediately above. . On the other hand, the third instruction address holding register 16 is a 1-word register that holds the most recently executed instruction address 30 (FIG. 2 d) held in the first instruction address holding register 11. Here, when the contents of the first instruction address holding register 11 are updated, the second instruction address register 20 is updated to the contents of the first instruction address holding register 11 before this update.
The value obtained by adding . Therefore, the contents of the first and second instruction address holding registers 20 are the same when no branch is taken, and have different values when a branch is taken. The comparator 15 compares the contents of the first and second instruction address holding registers 11.20 and sends the result to the stack control circuit 24. FIG. 2e shows the detection signal 32 in which the comparator 15 detects a mismatch. Signals A-A+ of each signal 28 to 32 in FIG. 2 3. B, B+1 indicates an instruction address. As a result of the above, the instruction address A+2
and B are stack memory 1 as instruction addresses before and after the branch.
7 is stored.

〔Effect of the invention〕

As explained above, the present invention detects the occurrence of a branch by comparing the address immediately before execution with the value obtained by adding 1 to this address, so there is an effect that there is no need to decode the branch instruction, and the instruction set This has the advantage that address trace information can be collected effectively using common hardware for different processors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an address trace circuit according to the present invention, and FIG. 2 is a timing diagram showing the operation of the device when an instruction address branches. 11...First instruction address holding register, 14
......+1 adder, 15...Comparator, 16...Third instruction address holding register, 17
...Stack memory, 20...Second instruction address holding register, 24
...Stack control circuit.

Claims (1)

[Claims] An address trace circuit provided in a central processing unit and storing addresses of a series of executed instructions, comprising: a first instruction address holding circuit that holds an address of an instruction immediately before execution; an addition circuit that adds 1 to the content held in the instruction address holding circuit; a second instruction address holding circuit that sets a value obtained by adding 1 to the address of the instruction immediately before execution, which is the addition result by the addition circuit; a third instruction address holding circuit that sets an instruction address immediately before execution held in the first instruction address holding circuit; and a third instruction address holding circuit that sets the address of the instruction immediately before execution held in the first and second instruction address holding circuits, and A comparator circuit that compares the value obtained by adding 1 to the address of the immediately previous instruction, and when the comparison result by this comparator circuit does not match, the first
and a stack for a plurality of words and a stack control circuit for storing the contents of a third instruction address holding circuit.