JPH04287231A - Microprocessor - Google Patents

Abstract

PURPOSE:To easily realize an instruction replacing processing without using any complicated hardware or software when it is required to generate trap interruptions at plural points. CONSTITUTION:After writing '1' in the trap information bit of an instruction code for which the generation of a trap interruption is required in advance, the trap information bit is checked in the instruction code in the executing stage of the instruction and, when the bit is '1', a trap request signal is sent to a processor control section to execute the trap interrupting process.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor capable of performing interrupt control.

0002

2. Description of the Related Art In a stored program type microprocessor, when debugging a program, it is often desired to stop the execution of the program after passing through an arbitrary program.

[0003] For this reason, conventional microprocessors
In order to generate a trap interrupt when an arbitrary program is passed, this is achieved by replacing the instruction at the address where you want to stop program execution with the trap instruction that generates the interrupt.

0004

[Problems to be Solved by the Invention] In the conventional microprocessor as described above, in order to replace the instruction code where a trap interrupt is desired to be generated with a trap instruction,
It is necessary to save the replaced instruction code in another area in order to restore it later.

[0005] Therefore, when it is desired to generate trap interrupts at a plurality of locations, the instruction replacement process becomes complicated.

[0006]

[Means for Solving the Problems] A microprocessor of the present invention fetches an instruction code including 1-bit trap information indicating whether or not to generate a trap interrupt and executes the fetched instruction code. The apparatus includes a checking means for checking trap information, and an interrupt generating means for generating an interrupt based on the result of the checking means.

That is, the microprocessor of the present invention includes an instruction execution stage that checks the trap information of an instruction code that includes 1-bit trap information indicating whether or not to generate a trap interrupt and sends a trap request signal; and a processor control unit that inputs the trap request signal from the instruction execution stage and executes an interrupt.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a format diagram showing an example of an instruction code used in the embodiment of FIG.

In FIG. 1, a processor control unit 1 includes an instruction code prefetch buffer 2, an instruction code stage 3 for performing pipeline processing, an operand address calculation stage 4, an operand data read stage 5, and an instruction execution stage 6. Control behavior.

The instruction code 10 is stored in the instruction code prefetch buffer 2 by instruction fetch and sent to the instruction code stage 3. The instruction code 10 is sequentially sent to each of the instruction code stage 3, operand address calculation stage 4, operand data read stage 5, and instruction execution stage 6 in synchronization with the internal clock 8.

The instruction execution stage 6 executes an instruction code 10 latched in an internal instruction code holding register 7.
The trap information bit 11 (see FIG. 2) inside is checked. As a result of checking, trap information bit 11 is “
1'', a trap request signal 9 is sent to the processor control unit 1 to request a trap interrupt.

When the processor control unit 1 receives the trap request signal 9, it executes trap interrupt processing.

[0014]

As explained above, in the microprocessor of the present invention, "1" is written in advance to the trap information bit of the instruction code in which a trap interrupt is to be generated. When you want to generate trap interrupts at multiple locations by checking the information bit and sending a trap request signal to the processor control unit to execute trap interrupt processing when the trap information bit is "1". Another advantage is that instruction replacement processing can be easily realized without using complicated hardware or software.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a format diagram showing an example of an instruction code used in the embodiment of FIG. 1;

[Explanation of symbols]

1 Processor control unit 2 Instruction code prefetch buffer 3 Instruction code stage 4 Operand address calculation stage 5
Operand data read stage 6 Instruction execution stage 7 Instruction code holding register 8 Internal clock 9 Trap request signal 10 Instruction code 11 Trap information bit

Claims (2)

[Claims] 1. Checking means for fetching an instruction code including 1-bit trap information indicating whether or not to generate a trap interrupt and checking the trap information when executing the fetched instruction code; 1. An interrupt generating means for generating an interrupt according to a result in the microprocessor. 2. An instruction execution stage for checking the trap information of an instruction code including 1-bit trap information indicating whether or not to generate a trap interrupt and transmitting a trap request signal; A microprocessor comprising: a processor control unit that inputs a trap request signal and executes an interrupt.