JP2687750B2 - Electronic computer processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to facilitating debugging,
The present invention relates to a processing device for a computer which decides to perform dynamic statistics collection of a program, a procedure call, or a process switch.

[0002]

2. Description of the Related Art Conventionally, it has been necessary to debug programs and collect dynamic statistics when developing electronic computers. Here, the dynamic statistics means, for example, obtaining the execution frequency or the execution time of a procedure or a process.

Breakpoints and traces are used to perform these debugging and dynamic statistics. Here, the break point is a method of knowing the execution state of the program by replacing some instructions such as branch instructions in the program with instructions for transferring control to a specific location. On the other hand, the trace is a method in which control is temporarily transferred to the operating system to record each time each instruction is executed for all instructions, and then control is transferred to the next instruction. You can see the details of the execution of.

Motorola processor (CPU)
The "MC68020" has an instruction called TRAP (trap) in order to observe the execution state of the program at the breakpoint.

FIG. 8 shows the main part of the configuration of this processor. The processor includes an instruction decoder 12 that receives and decodes an instruction 11 read from a memory (not shown). The decoding result of the instruction decoder 12 is supplied to each of the next instruction address calculator 13, the execution unit 14 and the trap controller 15.

Here, the execution unit 14 is for executing the decoded instruction, and the next instruction address calculator 13 is for calculating the address of the next instruction in order to read it. The address calculated by the next instruction address calculator 13 becomes one input of the instruction address multiplexer 16. The address output from the trap controller 15 is input to the other side of the instruction address multiplexer 16. The instruction address multiplexer 16 is controlled based on the control content of the trap controller 15, supplies one of these inputs as address information 17 to the memory described above, and uses it as address information at the time of reading the next instruction.

That is, in this processor, the instruction decoder 12 has a function as a normal decoder and
When a specific command is input, it is discriminated and the decoding result is supplied to the trap controller 15. In this case, the trap controller 15 outputs a special address for the trap and switches the address output by the instruction address multiplexer 16 to the trap controller 15 side. This realizes a trap for a specific instruction.

On the other hand, a processor "i4" manufactured by Intel Corp.
86 ”has a debug register that holds the address to be trapped as a variation of the breakpoint. Then, the contents of the debug register and the address are compared, and if they match, a trap is made.

Further, in the processor having the supervisor mode, the trace can be performed by setting the trace bit of PCW (processor control word). In this method, a trap is generated each time an instruction is executed in the user mode, and control is transferred to the trap handler in the supervisor mode.

[0010]

In the method by the processor "MC68020" among the above conventional techniques, in order to execute the trap, this instruction is incorporated into a required position (breakpoint) in the original program and executed. A rewritable memory is needed. In addition, there is a problem that the behavior of the program cannot be grasped at a place other than the place where the breakpoint is set.

Next, in the method using the debug register described in the processor "i486", addresses are compared, so that a rewritable memory is not required and a breakpoint can be set in a ROM (read only memory). . However, the behavior of the program cannot be understood except at the set breakpoints.

In this respect, the last-mentioned trace can grasp the behavior at each instruction step for the user mode program. However, since traps are generated for steps of unnecessary instructions and control is transferred to the trap handler one by one in the supervisor mode, it becomes a large overhead for the execution of the program under test.

Further, since the supervisor mode is used in this method, tracing cannot be performed for a processor that does not have this mode. The above-mentioned processor "MC68020" has a trace function for trapping only a branch instruction or a jump instruction in order to improve the overhead. However, in this case as well, in addition to the need for the supervisor mode, tracing is performed for instructions other than branch instructions and jump instructions, for example, for instructions such as procedure call and process switching, for which you want to understand the behavior of the program. I can't do it.

Therefore, an object of the present invention is to provide an electronic device capable of trapping instructions other than a branch instruction or a jump instruction, even in a processor without a supervisor mode, regardless of whether writing to a memory is possible or not. To provide a processing device for a computer.

[0015]

According to a first aspect of the invention, an instruction for controlling an electronic computer is input, and when a specific instruction of these instructions is input, at least one signal "1" is output. A decoder that outputs a bit pattern of one or more bits including one, and outputs a bit pattern in which all the bits are "0" in the case of other instructions.
The instruction address calculation means for calculating the instruction address to which control is transferred for each instruction and the instruction address calculated by this instruction address calculation means are input, and the bit of this bit string is always "0". An instruction address replacing means for replacing a specific position with a bit pattern, and a trap generating means for generating a trap when a bit pattern exists at a specific position of the instruction address replaced by the instruction address replacing means, and a computer processing device. Prepare for.

That is, according to the first aspect of the invention, the data at the specific position where the bit of the instruction address calculated by the instruction address calculation means is always "0" is replaced with a predetermined bit pattern. Here, this bit pattern is a pattern including at least one signal "1" for a specific instruction. The trap generation means will generate a trap when a bit pattern including the signal "1" exists at this specific position.

According to a second aspect of the present invention, one or a plurality of commands including at least one signal "0" when a command for controlling the electronic computer is input and a specific command among these commands is input. A decoder that outputs a bit pattern of bits and outputs a bit pattern in which all bits are "1" in the case of other instructions and an instruction address to which control is transferred for each instruction An instruction address calculating means, an instruction address replacing means for inputting the instruction address calculated by the instruction address calculating means, and replacing a specific position of the bit string where the bit is always "1" with a bit pattern, and the instruction address A trap generating means for generating a trap when a bit pattern exists at a specific position of the instruction address replaced by the replacing means. It is provided to the computer processing unit for.

That is, according to the second aspect of the invention, the data at the specific position where the bit is always "1" in the instruction address calculated by the instruction address calculation means is replaced with a predetermined bit pattern. Here, this bit pattern is a pattern including at least one signal "0" for a specific instruction. The trap generation means will generate a trap when a bit pattern including the signal "0" exists at this specific position.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.
FIG. 1 shows the basic configuration of the processing unit for electronic computers of this embodiment. This computer processing device is
An instruction decoder 21 for inputting an instruction 11 read from a memory (not shown) is provided. The first output of the instruction decoder 21 is the next instruction address calculator 22 and the XFE.
It is supplied to the R trap detector 23. The XFER trap is a trap by a specific instruction group. In the present embodiment, in addition to branch instructions and jump instructions, predetermined instructions such as procedure calls and process switching correspond to this.

The second output of the instruction decoder 21 is supplied to the execution unit 24, and the third output is supplied to the trap controller 25. The trap controller 25 controls the selection of the instruction address multiplexer 26 and outputs a trap address 27 for performing a trap. The instruction address multiplexer 26 outputs one of the next instruction address 28 output from the next instruction address calculator 22 and the trapping address 27 as address information 29 and supplies the address information 29 to the memory.

Further, an XTE flag generator 31 is provided in the processing unit for electronic computer of this embodiment. The XTE flag generator 31 is instructed by the execution unit 24 to
The XTE flag 32 having a predetermined bit pattern is supplied to the next instruction address calculator 22, and the predetermined bit string of the next instruction address 28 is replaced with the XTE flag 32.

In the processing device for electronic computer having the above-mentioned configuration, the XFER trap detector 23 sets the next instruction address 2
The contents of 8 are inspected to determine whether or not there is a predetermined bit pattern to be trapped. Then, if the same bit pattern as this exists at a predetermined bit position, the trap address 27 output by the trap controller 25 is output to the above-mentioned memory instead of the next instruction address 28.

In the processing unit for electronic computer of this embodiment, each stage such as instruction reading, decoding, execution, and next instruction address calculation may be pipelined so that efficient processing can be performed. . The calculation of the next instruction address may be performed by dedicated hardware for this calculation, or may be shared by those having different functions such as an instruction execution unit.
In short, it is sufficient that the calculation result can be modified by the XTE flag 32 in the address calculation of the next instruction.

The computer processing device of this embodiment employs a four-stage pipeline system in order to improve the processing efficiency.

FIG. 2 is for explaining the 4-stage pipeline. In this example, the pipeline consists of four stages: instruction fetch F, instruction decoder D, instruction execution E, and result writing W. Most instructions can be executed in one cycle, but some instructions require multiple cycles. In FIG. 2A, the call (C
All) takes 2 cycles to execute. FIG.
(B) shows the relationship between each fetched address and the called instruction as a change over time.

The instruction fetch stage includes the next instruction address calculator 22 and the XFER trap detector 2 shown in FIG.
3 and an instruction address multiplexer 26. The instruction decode stage is composed of an instruction decoder 21. The instruction execution stage includes an execution unit 24, an XTE flag generator 31 and a trap controller 25. The writing stage is
The execution unit 24 is used. That is, in the processing unit for a computer of this embodiment, the execution unit 24 is shared by the execution stage and the writing stage.

FIG. 3 shows the configuration of the next instruction address calculator. The next instruction address calculator 22 includes a program counter 41. The value 42 of the program counter 41 is sent to the execution unit 24 (FIG. 1) to save the return address, and is also supplied to one input terminal of the first multiplexer 43. Address information 44 is supplied from the execution unit 24 to the other input terminal of the first multiplexer 43. The addition output of the first multiplexer 43 becomes one input of the adder 45.

The next instruction address calculator 22 has a second
The multiplexer 46 is provided, and the addition output thereof is the other input of the adder 45. Here, the second
The address information 44 is input from the execution unit 24 and the bit string representing the numerical value "4" is input from the circuit (not shown) to the multiplexer 46. The first and second multiplexers 43 and 46 are controlled by the control signal 48 from the instruction decoder 21 (FIG. 1).

The output side of an AND gate 49 is connected to the adder 45. This AND gate 49 is XTE
The flag value 51 and the control signal 52 from the instruction decoder 21 are logically ANDed. Here, the control signal 52 is set to "1" while the processing unit for electronic computer outputs the instruction for generating the XFER trap. Adder 45
In addition to being input to the program counter 41, the output of is sent to the XFER trap detector 23 and the instruction address multiplexer 26 as the output of the next instruction address calculator 22 as shown in FIG.

By the way, the address of the CPU is in byte units, but in this embodiment, the width of each word of the instruction is 4
It is fixed on the bite. Therefore, in the apparatus of this embodiment, each instruction is set to start at an address divisible by the numerical value "4". This means that the lower 2 bits of the program counter 41 are always "0".

When there is no instruction that causes an XFER trap such as procedure call or process switching, the first and second multiplexers 43 and 46 are controlled by the instruction decoder 21 so as to output the inputs on the left side of each other in the figure. Has been done. For this reason, in this case, the value 42 of the program counter 41 is added by "4" by the adder 45 and becomes the output of the next instruction address calculator 22, and at the same time, the program counter 41 is updated to the next cycle. ing.

In a state where such a trap is not generated, the value 51 of the XTE flag is masked by the AND gate 49 by the control signal 52 from the instruction decoder 21. Therefore, the carry-in input C _in from the AND gate 49 to the adder 45 is always “0”, and the adder 4
The lowest of the calculated next instruction address 28 output from 5 is "0".

Instructions such as a jump instruction and a call instruction are summed with a register (not shown) existing in the execution unit 24 and used as a destination address. Lower 2 at this time
The bit is set to be "0". In the case of an instruction such as a jump instruction or a call instruction, the instruction decoder 21 outputs the input on the right side in the figure in the first and second multiplexers 43 and 46, and the address information 44 as the value of the register of the execution unit 24 is added to the adder 45. Will be given to.

On the other hand, when there is an instruction that causes an XFER trap, the instruction decoder 21 sets the control signal 52 to "1", and the value 51 of the XTE flag is input as the carry-in input C _in of the adder 45. Therefore, in this state, an instruction that causes an XFER trap, such as a procedure call or process switching, causes an XTE
When the flag becomes "1", the LSB (least significant bit) of the calculated next instruction address 28 output from the adder 45
Becomes "1".

FIG. 4 shows the structure of the XFER trap detector. The XFER trap detector 23 is
An OR gate 61 for inputting the lower 2 bits of the next instruction address 28 output from the adder 45 shown in FIG. 3 and an AND gate 62 for inputting the least significant bit to one input terminal.
It is composed of The control signal 52 from the instruction decoder 21 is supplied to the other input terminal of the AND gate 62.
(See FIG. 3) is input.

In the XFER trap detector 23, the output of the AND gate 62 is sent to the XFER trap request signal 64.
And That is, the XFER trap request signal 64
Indicates a cycle in which an XFER trap can occur, looks at a specific bit pattern (here, LSB) of the calculated next instruction address 28, and when this bit is "1", X
Make a FER trap request.

By the way, in this computer processor, the lower 2 bits of the instruction address must be "0" without causing a trap. So OR gate 6
1 takes the logical sum of the lower 2 bits, and when it becomes "1", it is supposed that an illegal address is generated and a trap is generated. At this time, if the least significant bit is "1", it can be almost inferred that it is due to the XFER trap.

Next, consider the case of executing the instruction shown in FIG. The call instruction existing at the address “A1” is R _X
This is an instruction that can generate an XFER trap by saving the return address in R _Z using the sum of R and R _Y as the destination address. If an XFER trap occurs, go to the address "A20" where the XFER trap handler exists, and if it does not occur, go to the address "A" with the procedure entry.
Go to 10 ".

This CPU adopts a delayed branch system, and executes the instruction at the address "A2" instead of immediately going to the address "A20" or the address "A10" after executing the instruction at the address "A1". Since then, I have been going to one of these addresses.

FIG. 2A shown above shows the state of each stage of the pipeline when the call instruction is executed. The call instruction requires two cycles to execute, and R _X + R _Y is calculated in the first cycle. Then, in the second cycle, the return address is saved in R _Z. The instruction memory access is pipelined as shown in FIG. Therefore, when the memory outputs the instruction word, the memory receives the address of the next instruction.

The address "A1" of the call instruction is shown in FIG.
When output in the F stage of (a), this call instruction is fetched. In the next cycle, the address "A2" is output at the F stage and the I ₂ instruction is fetched. At the same time, the call instruction is decoded. Since the call instruction requires two cycles to execute, the instruction decoder 21 (FIG. 1) instructs the next instruction address calculator 22 to pause for one cycle.

In the next cycle, the next instruction address calculator 2
2 calculates R _X + R _Y. At this time, the XTE flag is input as the carry-in input C _in of the adder 45.

When the XTE flag is "1", the LSB of the next instruction address calculator 22 is "1". Therefore, the output of the AND gate 62, that is, the XFER trap request signal 64 becomes "1" in the XFER trap detector 23, and the XFER trap is requested to the trap controller 25.

The trap controller 25 determines the address of the XFER trap handler, that is, the address "A2.
0 "is generated and given to the instruction address multiplexer 26. Also, this instruction address multiplexer 26
To the trap address side, and the address "A20"
To the instruction memory (not shown) to fetch the I ₂₀ instruction. This means that the XFER trap has been achieved.

(First Modification) In the embodiment described above, the modification by the XTE flag is the least significant bit of the address. However, the modification is not limited to this and may be the most significant bit, for example. Such a modification method can be used, for example, when configuring a computer processing device in which instruction words are aligned on the addressable minimum unit boundary.

FIG. 6 shows a memory space used in this first modification. The memory space 71 is an instruction space 72 from address “0” to address “M”,
XF from address "M + 1" to address "MAX"
It is divided into a space 73 for ER trap detection.

In this modification, the memory space 71 seems to have been halved at first glance. However, XF
The XFER trap detection space 73 used for detecting an ER trap is used for address calculation for instruction fetch and is not related to data address calculation. Therefore, the XFER trap detection space 73 can be used for storing data, and no waste occurs.

(Second Modification) In a certain computer architecture, the upper half and the lower half of the address may be divided into a user space and a supervisor space. In such a case, the XTE flag modifies the second bit from the top of the address.

FIG. 7 shows a memory space in the second modification. The memory space 81 includes a user instruction space 82, a user data and XFER trap detection space 83, and a supervisor instruction space 8
4 and supervisor data and space 85 for XFER trap detection.

The second modification is an example of a processor having a supervisor mode. However, in the case of this modification, it is not necessary to switch to the supervisor mode each time a trap occurs. The control will be simplified.

(Other Modifications) In the embodiment, XTE is used.
The flag generator 31 was used to generate the XTE flag, but the XTE flag was placed in the register that outputs to at least one of the two inputs to the adder 45 of the next instruction address calculator 22.
A flag may be provided. XT of this register
The part other than the E flag may be "0", or may have information for address calculation. In this case, a register having an XTE flag will be used for address calculation to perform a procedure call or process switch.

Such a technique can also be realized by using a commercially available processor equipped with an illegal address detector. For example, although it is addressed in bytes, instruction words are always placed on 4-byte boundaries,
The lower 2 bits of the address as the instruction address are "0"
Other than that, consider a processor that generates a trap as an illegal address. In such a processor,
An XFER trap can be realized by putting XTE in at least one of the lower two bits of the address when calculating the instruction address for the procedure call or the process switching.

In this case, the illegal address detector is X
It is operating as a FER trap detector. Therefore, the XFER trap is detected as an illegal address trap that the processor originally had.

Further, in the embodiment, by inputting carry-in input C _in from AND gate 49 to adder 45, XFE
I tried to detect the R trap,
It is also possible to provide two registers corresponding to the two inputs, and store a bit pattern for XFER trap detection in one of them. Then, a trap is generated by adding this bit pattern to the adder 45. Further, the destination address of the procedure or process for the jump instruction or call instruction is set by taking the sum of the contents of these two registers.

This modification can also be realized by software. For example, it is assumed that there is a jump (JUM) instruction or a call (CALL) instruction whose effective address is the sum of the contents of the above two registers. Now, it is assumed that the destination address of the procedure or process is stored in the first register "R0" and the XTE flag is stored in the second register "R1". In this case, "JMP" R
0 ”+“ R1 ”” or “CALL“ R0 ”+“ R
If the bit pattern to be trapped is detected as "1"", the present invention can be realized.

Further, for the detection of the XFER trap, the illegal instruction address detection mechanism which some processors conventionally have, and the memory protection and page fault detection mechanism which the MMU (memory management unit) has are diverted. You can also When these mechanisms detect a predetermined condition, they will trap or interrupt the processor to inform that the condition is met.

This modified method is convenient for realizing the present invention when a processor having a memory management function or a processor not having the memory management function is added and used.

In the embodiment, the description has been made on the assumption that the portion where the instruction address calculated by the instruction address calculating means is always "0" is replaced with the bit pattern having at least one signal "1". On the contrary, it is also possible to replace the portion where "1" is always arranged with a bit pattern in which at least one signal "0" exists.

[0059]

As described above, according to the present invention, a portion of the instruction address calculated by the instruction address calculating means, which always shows a constant value, is replaced with a bit pattern different from this. Therefore, it is possible to trap the necessary instruction regardless of the presence or absence of the supervisor mode. Moreover, since it is decided to perform the trace by performing the address operation, it is not necessary to rewrite the contents of the memory. Further, according to the present invention, there is an effect that a predetermined instruction such as a procedure call can be detected with a small overhead.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a configuration of a processing device for an electronic computer according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the timing when an instruction is executed in the device of this embodiment.

FIG. 3 is a block diagram showing a configuration of a next instruction address calculator of this embodiment.

FIG. 4 is a circuit diagram showing a configuration of an XFER trap detector of this embodiment.

FIG. 5 is an explanatory diagram showing a part of instructions in the present embodiment.

FIG. 6 is an explanatory diagram showing a memory space in a first modified example.

FIG. 7 is an explanatory diagram showing a memory space in a second modified example.

FIG. 8 is an explanatory diagram showing an outline of a configuration of a conventional processor.

[Explanation of symbols]

21 ... Instruction decoder, 22 ... Next instruction address calculator, 2
3 ... XFER trap detector, 24 ... Effective unit, 2
5 ... Trap controller, 26 ... Instruction address multiplexer, 41 ... Program counter, 43, 46 ... Multiplexer, 45 ... Adder, 49 ... AND gate

Claims (2)

(57) [Claims] 1. A command for controlling an electronic computer is input, and when a specific command among these commands is input, a bit pattern of one or a plurality of bits including at least one signal "1" is output. However, in the case of other instructions, a decoder that outputs a bit pattern in which all bits are "0", and an instruction address calculation unit that calculates an instruction address to which control is transferred for each instruction, Enter the instruction address calculated by this instruction address calculation means,
An instruction address replacement unit that replaces a specific position of the bit string where the bit is always "0" with the bit pattern, and the bit pattern exists at the specific position of the instruction address replaced by the instruction address replacement unit. And a trap generating means for generating a trap when the processing is performed. 2. A command for controlling a computer is input, and when a specific command among these commands is input, a bit pattern of 1 or more bits including at least one signal "0" is output. However, in the case of other instructions, a decoder that outputs a bit pattern in which all bits are “1”, and an instruction address calculation unit that calculates an instruction address to which control is transferred for each instruction, Enter the instruction address calculated by this instruction address calculation means,
An instruction address replacement unit that replaces a specific position of the bit string where the bit is always "1" with the bit pattern, and the bit pattern exists at the specific position of the instruction address replaced by the instruction address replacement unit. And a trap generating means for generating a trap when the processing is performed.