JPS59200343A - Microprogram controller - Google Patents

Abstract

PURPOSE:To attain processing for the interruption of an asynchronous phenomenon without using an interruption trap address generating circuit, by controlling the interruption detection timing by the contents of an instruction control field provided into a microinstruction. CONSTITUTION:If an interruption request produced by an asynchronous phenomenon does not exist in an interruption factor register 6, a selection circuit 5 selects the contents of the next address field of the microinstruction which is presently read out of a microinstruction register 2. Then the address is decided for the microinstruction to be executued next. An interruption request corresponding to an asynchronous factor is registered into an interruption factor register 6, and an interruption control field of the microinstruction read out to the register 2 indicates the permission of interruption. In such a case, the circuit 5 selects the output of an address register 4. As a result, the microinstruction in the address next to the microinstruction which is presently executed is read out as the microinstruction to be executed next.

Description

[Detailed description of the invention] The present invention relates to a microprogram controller.

While an information processing device using a microprogram is executing a microinstruction, an asynchronous event (firmware interrupt) occurs, such as an error report from main memory or a request for communication from another processor, which is currently being executed. Change the micro-separation sequence of j1! If it is necessary to interrupt (interruption), generally the hardware is forced to generate a specific address storing the next microinstruction to be executed and trap to that address.

This specific address stores a group of microinstructions for processing an asynchronous event, ie, the first microinstruction of an interrupt processing routine. This interrupt handling routine is
Read the contents of the interrupt cause register and analyze the contents,
Perform necessary processing.

When the interrupt processing is completed, control is passed to another routine or returned to the routine that detected the asynchronous event.

In order to perform interrupt processing for such asynchronous events, conventional devices use a hardware interrupt trap address generation circuit to trap at a specific trap address as described above. The address depends on the hardware.
Since it is generated directly, it must be fixed, and therefore has the disadvantage of lacking flexibility in creating microprograms.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly flexible microprogram control system that handles interrupts of asynchronous events without using an interrupt trap address generation circuit.

The apparatus of the present invention includes a control storage means for storing all microprograms, a microinstruction storage means for storing companion microinstructions read from the control storage means, and a microinstruction storage means to be executed next in the microinstruction storage means each time a microinstruction is executed. an addition means for adding 1 to the content of a first field containing the address of the microinstruction to be performed; an addition result storage means for storing the addition result of the addition means; and an event cause storage means for storing and holding cause information of the asynchronous event. and when the second field containing information for controlling reception of interrupts for the asynchronous event in the microinstruction storage means is a predetermined value and the contents of the event cause storage means are a predetermined value, the addition is performed. When all the outputs of the result storage means are selected and the second field in the microinstruction storage means does not have a predetermined value or the contents of the event cause storage means do not have a predetermined value, the output of the microinstruction storage means selection means for selecting the output of the first field, and the output of the selection means is used to specify the address of the microinstruction stored in the control storage means to select the next microinstruction to be executed. is read into the microinstruction storage means.

Next, the present invention will be described in detail with reference to the drawings.

As shown in FIG. 1, an information processing system generally includes a plurality of processors Po, Pl, P2, etc. Taking processor po as an example, this processor po for other processor PIs.

P2... are respectively lines t1 + t2...
Issue a communication request via... These are handled as asynchronous interrupts as necessary. It's not Kasi, it's
Processor Po includes an asynchronous event detection circuit for detecting, for example, a parity error in a data register, and when detected, it is similarly processed as an asynchronous interrupt.

The present invention provides an apparatus for flexibly handling such asynchronous interrupts.

With full reference to FIG. 2, one embodiment of the present invention provides control capability tf
&(C”')L Microinstruction Register (MIR) 2.1
Addition circuit 3, address register (Al1, selection circuit 5,
It includes an interrupt cause register circuit (INTR) 6 and an AND gate 7.

The operation of this embodiment is as follows.

The microinstructions to be executed are read from the control store (C8) 1 and loaded into the microinstruction register (MIR, ) 2.

Each microinstruction has a netast address field (NA) that indicates the address in the control memory (C8) 1 of the next microinstruction to be executed, and an interrupt control field (NA) that controls whether to enable or disable asynchronous interrupts. T).

The output of the netast address field (NA) portion of the microinstruction register (MIR) 2 is supplied to one input of the selection circuit 5 and the input of the 1 adder circuit 30.

The i7JII arithmetic circuit 3 adds 1 to the contents of the supplied next address field (NA), stores this in the address register (AR) 4, and supplies this to the other input of the selection circuit 5.

On the other hand, the output (T bit output) of the interrupt control field (T) (1 bit in this embodiment) is supplied to the AND gate 7 along with the output of the interrupt cause register circuit (INTR) 6. , the output of this AND gate 7 is supplied to the selection circuit 5 as a selection control signal.

When the output of the door/dog door is altt, the selection circuit 5 selects the output of the address register (AR) 4 and sets it to 0''.
In this case, the output of the next address field (NA) of the microinstruction register (MIR) 2 is selected. Then, the selected output is supplied to the control memory (C8) 1 as read address designation information, and the microinstruction to be executed next is specified by the microinstruction register (Ml).
Read to z.

Now, if there is no interrupt request caused by an asynchronous event in the interrupt cause register circuit (INTR) 6, the output of the circuit (INTR) 6 becomes uO''.

Therefore, if the content of the interrupt control field (T) is uO'' indicating that interrupts are not permitted, or if there is no interrupt request due to an asynchronous event, the selection circuit 5 currently selects the microinstruction register (MIR). The contents of the next address field (NA) of the microinstruction read out in step 2 are selected, and the address of the microinstruction to be executed next is determined based on this.

Thus, in this case, as in the past, the microinstructions at the addresses in the control memory (C8) specified by the next address field (NA) of each microinstruction are read out and executed one after another, and thus the microprogram 2 Processing proceeds according to the sequence specified by the system.

Now, an interrupt request corresponding to the asynchronous cause is registered in the interrupt cause register circuit (INTJ6), and the interrupt control field (T) of the microinstruction read into the microinstruction register (MIR) 2 is u1''. If interrupt permission is instructed by , the output of AND gate 7 will be u1'',
The selection circuit 5 selects the output of the address register (AR) 4, and as a result, the microinstruction at the address next to the microinstruction currently being executed is read out as the next microinstruction to be executed. Therefore, by making this microinstruction the first microinstruction in a microprogram routine that handles asynchronous interrupts (or a jump instruction that jumps to the start address of the processing route), the normal microprogram sequence is interrupted and this A routine may be started to handle asynchronous interrupts.

That is, according to this embodiment, for each microinstruction convenient for accepting an asynchronous interrupt in a microprogram, the interrupt control field (T) is set to '1', and the microprogram is stored in the control memory (O8) 1. When storing u1'', this interrupt control field (T)
By setting the next address of the microinstruction marked as the start address of the interrupt processing microprogram routine, when an interrupt request is received, the interrupt is accepted immediately after execution of this microinstruction, and interrupt processing is started. can do. In this case, the method of selecting the microinstruction that allows interrupt acceptance can be freely determined when creating the microprogram, so it is highly flexible.
Allows processing of asynchronous interrupts.

FIG. 3 is a diagram showing the embodiment in further detail.

The interrupt cause register circuit 6 has an interrupt cause register 60 and an interrupt cause register 61, and interrupt requests due to the causes of each asynchronous event described above are registered in corresponding predetermined pits of the register 60.

The outputs of each bit of the register 60 are all ORed by an OR gate 61 and supplied to one input of an AND gate 7.

In addition, the selection circuit 5 includes an inverter 50, an andgoo 451
-1.51-2. ...51-N, 51-1'
.

51-2',..., 51-N' and or gate 52-1.52-2.・・・・・・52-N (However, N
, N' is the bit width of the next address field (NA)].
If the door output is 10°2, the next address field (NA) of microinstruction register (MIR) 2
Select and output the bit in the part, and if the output of the address register (AR) is u1'',
4 is selected and output, and this is stored in the control memory (C8
)H is supplied to the control memory (C8) 1 as addressing information.

Next, FIG. 4(A) and FIG. 4(B) show the operation of this embodiment as a time chart.

FIG. 4(A) shows the operation when there is no interrupt request (when the output of the OR gate 61 in FIG. 3 is uO'').

Although not shown in Figure 3, the microinstruction register (
A machine clock is supplied to MIR) 2 and address register (AR) 4, and data to these registers is latched at the leading edge of the rising edge of the machine clock as shown in FIG.

Now, microinstruction A is stored in microinstruction register (MIR) 2 at point [o] (A, which specifies the microinstruction, uses the memory address where the microinstruction in control memory (C8) 1 is stored) Assume that the contents of the netast address field (NA) of this instruction A are B.

Since there is no interrupt request, the output of OR gate 61 is 10''.
Therefore, the output of the AND gate 7 is uO'', and the selection circuit 5 selects the contents of the next address field (NA) of the microinstruction register (MIR) 2, and the output of the AND gate 7 is uO''. Output this value B. As a result,
The control memory (C8) 1 outputs the microinstruction at memory address B, which is latched into the microinstruction register (MIR) 2 at the next rising edge of the machine clock. Assuming that the content of the next address field (NA) of microinstruction B is C, microinstruction C is read from control memory (C8) 1 at the next rising edge of the machine clock in exactly the same way as described above. It is latched into register (Mi)2. For example, suppose the content of the next address field (NA) of microinstruction C is D, and among microinstructions A, B, C, and D, only C has ult) in its interrupt control field (T). T pit output for 1 machine clock from t2 is 1
1'', but the output tlO'' of AND gate 7 does not change, and in exactly the same way as above, the next address field (NA) of microinstruction C is specified at time t3 at the rising edge of the next machine clock. The microinstruction register is read from the control memory (C5) 1 and stored in the microinstruction register (MI
R) is latched to 2. In this way, if there is no interrupt request, the microprogram is executed according to the sequence specified by each microinstruction even if the interrupt control field (T) is u1''.

Note that the contents of the address register (AR) 4 are latched at the next machine clock by adding 1 to the contents of the netast address field (NA) read to the microinstruction register (MIR) 2. For example, Figure 4 (
A) As is clear, the microinstruction register (MI
In the machine cycle in which microinstruction C is read at R)2, the contents of address register (AR)4 are C+1.
The value of will be retained.

Next, the time chart of FIG. 4(B) shows the operation when an interrupt request occurs (when the output of the OR gate 61 of FIG. 3 becomes ul'').

Up to the time of machine clock t2, the process is exactly the same as the case in FIG. (MIR) 2, and the interrupt control field (T) of this instruction is 5'l'', so the output of the anodog door is ul'', and as a result,
The selection circuit 5 receives the output C+1 of the address register (AR) 4.
In order to select
It is latched into the microinstruction register (MIR) 2 at the point in time. If the next address field (NA) numerator of this microinstruction C+1 is o, and the interrupt control field C'I') is tlO'', then the next machine cycle t
At step 4, the microinstruction To is read into the microinstruction register 2, and thus the microprogram branches to an interrupt processing routine whose starting address is C+1.

That is, the netast address field (NA) of microinstruction C is D, and if there is no interrupt request, ic td
, As explained in FIG. 4(A), the microprogram progresses as microinstructions A, B, C, D, etc., but if there is an interrupt request, the microprogram progresses as shown in FIG. 4(A). As shown in B), the microprogram consists of microinstructions A, B, and C.
,C+1. By proceeding as TQ... and selecting C+1〆D, the microprogram branches to the interrupt processing routine with C+1 as the starting address.

As described above, according to the present invention, without using a hardware-based trap address generation circuit for interrupts,
A flexible microprogram controller can be provided that is free to handle interrupts of asynchronous events using a specific configuration of microinstructions in control memory.

According to the present invention, the timing at which interrupts are detected can be controlled by the contents of an interrupt control field provided in a microinstruction, so interrupts can be freely masked as necessary without using special hardware. In addition, it is possible to predict in advance what type of interrupt will occur depending on its detection position in the microprogram, and in this case, it is easy to analyze the cause in the interrupt processing routine. You can also.

Furthermore, the 1 addition circuit used in the present invention is
A reduction in hardware can be achieved by sharing the 1-adder circuit for generating the call return address.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the occurrence of an asynchronous event, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing the embodiment in more detail, and FIG. ) and FIG. 4 are time charts for explaining the operation of this embodiment. In fig. 1... Control memory (C8), 2... Micro instruction register (1viIRJ, 3...l
771] Arithmetic circuit, 4...Address register (A
R), 5... Selection circuit, 6... Interrupt cause register circuit (INTR,), 7... AND gate, 50... Inverter, 51 -1 to 51
-N, 511/~51-N'...AND gate, 52-1~52-N...OR gate, 60.
...Interrupt cause register, 61...OR gate〇

Claims (1)

[Claims] Control storage means for storing a microprogram. microinstruction storage means for storing a microinstruction read out from the control storage means; and a first field containing a microinstruction address to be executed next in the microinstruction storage means each time a microinstruction is executed. an addition means for adding; an addition result storage means for storing the addition result of the addition means; an event cause storage means for storing and holding cause information of the asynchronous event; Information that controls reception? When the second field containing a predetermined value and the contents of the event cause storage means have a predetermined value, the output of the addition result storage means is selected and the second field in the microinstruction storage means has a predetermined value. a selection means for selecting the output of the first field in the microinstruction storage means when the value is not a predetermined value or when the content of the event cause storage means is not a predetermined value, and the output of the selection means is used. 2. A microprogram control device according to claim 1, wherein a microinstruction to be executed next is read into the microinstruction storage means by specifying an address of a microinstruction stored in the control storage means.