JPS6392959U - - Google Patents
Info
- Publication number
- JPS6392959U JPS6392959U JP18796486U JP18796486U JPS6392959U JP S6392959 U JPS6392959 U JP S6392959U JP 18796486 U JP18796486 U JP 18796486U JP 18796486 U JP18796486 U JP 18796486U JP S6392959 U JPS6392959 U JP S6392959U
- Authority
- JP
- Japan
- Prior art keywords
- data
- input port
- external input
- rom
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本案の概略図、第２図は本案の一実施
例を示す図、第３図は本案のタイムチヤートを示
す。
１……マイクロコンピユータ、２……ＲＯＭ、
３……アドレス検知回路、４……ＲＯＭ一外部切
換スイツチ、５……データバス切換、６……入力
ポート、７……アドレススイツチ、８……ＲＡＭ
、９……Ｉ／ＯＩＣ。
FIG. 1 is a schematic diagram of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a time chart of the present invention. 1...Microcomputer, 2...ROM,
3... Address detection circuit, 4... ROM-external switching switch, 5... Data bus switching, 6... Input port, 7... Address switch, 8... RAM
, 9...I/OIC.
Claims (1)
ータが格納されたＲＯＭ，ＲＡＭ，拡張Ｉ／ＯＩ
Ｃからなるマイクロコンピユータシステムにおい
て、ＲＯＭの実装用ソケツトに接続し、かかるＲ
ＯＭのアドレス空間内の任意のアドレスのＲＯＭ
のデータの代わりに、外部入力ポートからデータ
を入力することを特徴とするデバツグ装置。 ２ 請求の範囲第１項において、ＲＯＭのデータ
と外部入力ポートとの切換を行なうスイツチを設
けたことを特徴とするデバツグ装置。 ３ 請求の範囲第１項において、外部入力ポート
の値をマイクロコンピユータの機械語のインスト
ラクシヨンコードとすることを特徴とするデバツ
グ装置。[Claims for Utility Model Registration] 1. Microcomputer, ROM in which programs and data are stored, RAM, expansion I/OI
In a microcomputer system consisting of C, the R
ROM at any address within the OM address space
A debugging device characterized in that data is input from an external input port instead of data from the external input port. 2. The debugging device according to claim 1, further comprising a switch for switching between ROM data and an external input port. 3. The debugging device according to claim 1, wherein the value of the external input port is an instruction code in machine language of a microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18796486U JPS6392959U (en) | 1986-12-08 | 1986-12-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18796486U JPS6392959U (en) | 1986-12-08 | 1986-12-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6392959U true JPS6392959U (en) | 1988-06-15 |
Family
ID=31138900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18796486U Pending JPS6392959U (en) | 1986-12-08 | 1986-12-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6392959U (en) |
-
1986
- 1986-12-08 JP JP18796486U patent/JPS6392959U/ja active Pending