JPS6314192U - - Google Patents
Info
- Publication number
- JPS6314192U JPS6314192U JP10752386U JP10752386U JPS6314192U JP S6314192 U JPS6314192 U JP S6314192U JP 10752386 U JP10752386 U JP 10752386U JP 10752386 U JP10752386 U JP 10752386U JP S6314192 U JPS6314192 U JP S6314192U
- Authority
- JP
- Japan
- Prior art keywords
- current time
- capacity
- rom
- stores
- time data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
- 101100328887 Caenorhabditis elegans col-34 gene Proteins 0.000 description 3
- RRLHMJHRFMHVNM-BQVXCWBNSA-N [(2s,3r,6r)-6-[5-[5-hydroxy-3-(4-hydroxyphenyl)-4-oxochromen-7-yl]oxypentoxy]-2-methyl-3,6-dihydro-2h-pyran-3-yl] acetate Chemical compound C1=C[C@@H](OC(C)=O)[C@H](C)O[C@H]1OCCCCCOC1=CC(O)=C2C(=O)C(C=3C=CC(O)=CC=3)=COC2=C1 RRLHMJHRFMHVNM-BQVXCWBNSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Electric Clocks (AREA)
Description
第１図は、本考案の一実施例の回路ブロツク図
、第２図ａ，ｂは、ＲＡＭ４及びＲＡＭ５の内部
構成を示す図、第３図ａは、システム全体の処理
の流れを示すフローチヤート、第３図ｂは、モー
ド変換処理及びページ変換処理を説明するための
図、第４図ａは、計時処理におけるＲＡＭ４、Ｒ
ＡＭ５の動作説明を行うためのタイミングチヤー
トを示す図、第４図ｂは、ページ更新処理におけ
るＲＡＭ４、ＲＡＭ５の動作説明を行うためのタ
イミングチヤートを示す図である。
３……タイミングジエネレータ、４，５……Ｒ
ＡＭ、６……キー入力部、８……ＲＯＭ、１４…
…算術論理演算回路。
FIG. 1 is a circuit block diagram of an embodiment of the present invention, FIGS. 2a and 2b are diagrams showing the internal configuration of RAM4 and RAM5, and FIG. 3a is a flowchart showing the process flow of the entire system. , FIG. 3b is a diagram for explaining mode conversion processing and page conversion processing, and FIG. 4a is a diagram for explaining the RAM4, R
FIG. 4b is a diagram showing a timing chart for explaining the operation of the AM5, and FIG. 4b is a diagram showing a timing chart for explaining the operation of the RAM4 and RAM5 in page update processing. 3...timing generator, 4,5...R
AM, 6...Key input section, 8...ROM, 14...
...Arithmetic logic circuit.
Claims (1)
ＡＭと、 現在時刻データ以外のデータを記憶する大容量
ＲＡＭと、 マイクロプログラムを記憶するＲＯＭと、 該ＲＯＭに記憶されているマイクロプログラム
の制御により、 前記小容量ＲＡＭ内の現在時刻データを読出し
て現在時刻を更新する現在時刻作成手段と、 前記ＲＯＭから前記大容量ＲＡＭのアクセスを
行うためのマイクロ命令を出力させる信号を作成
するスイツチ手段と、 前記マイクロ命令により、前記大容量ＲＡＭの
アクセスを可能とする制御信号を前記大容量ＲＡ
Ｍに出力する制御手段とを備えたことを特徴とす
る電子時計。[Scope of claim for utility model registration] Small capacity R that stores at least current time data
AM, a large-capacity RAM that stores data other than the current time data, a ROM that stores a microprogram, and reads out the current time data in the small-capacity RAM under the control of the microprogram stored in the ROM. current time creation means for updating the current time; switch means for creating a signal for outputting a micro-instruction for accessing the large-capacity RAM from the ROM; and the micro-instruction enables access to the large-capacity RAM. The large capacity RA
An electronic timepiece characterized by comprising a control means for outputting an output to M.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10752386U JPS6314192U (en) | 1986-07-14 | 1986-07-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10752386U JPS6314192U (en) | 1986-07-14 | 1986-07-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6314192U true JPS6314192U (en) | 1988-01-29 |
Family
ID=30983882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10752386U Pending JPS6314192U (en) | 1986-07-14 | 1986-07-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6314192U (en) |
-
1986
- 1986-07-14 JP JP10752386U patent/JPS6314192U/ja active Pending
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