JPH0452222U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a block diagram of the configuration of a computer based on this invention, Figure 2 is an operational timing chart of a computer based on this invention, Figure 3 is a configuration diagram of a conventional computer, and Figures 4 and 5 are a diagram of a conventional computer. This is an operation timing chart, in which 1 is a CPU, 2 is a clock generation circuit, 3 is an address decoder, 4 is a memory, 5 is a wait control circuit, 6 is a memory read signal, 7 is an address signal, and 8 is a chip. Select signal, 9 is wait signal 1, 10 is wait signal 2, 11 is clock signal, 12 is data, 13 is driver, 14 is relay drive signal, 15
is a relay, 16 is a resistor, 17 is a voltage conversion circuit, 1
8 is a voltage signal, and 19 is a V/F conversion circuit. In the drawings, the same or corresponding parts are designated by the same reference numerals.

Claims (1)

[Scope of utility model registration request] A CPU that performs calculations and control, a memory that stores data, an address decoder that inputs address signals and memory read signals from the CPU and outputs chip select signals that select memory, and the CPU.
V/F (vol
t to Frequency) The frequency of the clock signal supplied to the CPU using the V/F conversion circuit in a computer consisting of a conversion circuit, a driver that converts the chip select signal into a relay drive signal, and a voltage conversion circuit consisting of a relay and a resistor. A calculator characterized by making variable.