JPH03110527U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a block diagram of the configuration of a computer based on this invention, Figure 2 is an operational timing chart of a computer based on this invention, Figure 3 is a configuration diagram of a conventional computer, and Figures 4 and 5 are conventional computers. FIG. 2 is a diagram of an operation timing chart of FIG. In the figure, 1 is the CPU, 2 is the clock generation circuit, and 3
is an address decoder, 4 is a memory, 5 is a wait control circuit, 6 is a memory read signal, 7 is an address signal, 8 is a chip select signal, 9 is a wait signal 1, 10 is a wait signal 2, 11 is a clock signal, 12 is a data, 13 is a decoder, 1
4 is a count value setting signal, 15 is a down counter, 16 is a synchronization circuit, 17 is a frequency dividing circuit, and 18 is a variable clock signal. In the drawings, the same or corresponding parts are designated by the same reference numerals.

Claims (1)

[Scope of utility model registration request] A CPU that performs calculations and control, a memory that stores data, an address decoder that receives address signals and memory read signals from the CPU, and outputs chip select signals that select memory;
a clock generation circuit that supplies a clock signal;
A frequency dividing circuit is used in a computer consisting of a frequency dividing circuit consisting of a down counter and a synchronization circuit that converts the frequency of a clock signal, and a decoder that sends a count value setting signal that is a signal that controls the count value of the down counter. A computer characterized in that the frequency of a clock signal supplied to a CPU is made variable.