JPS62146247U - - Google Patents
Info
- Publication number
- JPS62146247U JPS62146247U JP1986026598U JP2659886U JPS62146247U JP S62146247 U JPS62146247 U JP S62146247U JP 1986026598 U JP1986026598 U JP 1986026598U JP 2659886 U JP2659886 U JP 2659886U JP S62146247 U JPS62146247 U JP S62146247U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- microprocessor
- data bus
- data
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は第１図の要部ブロツク図、第３図と第４図と
は第１図に用いられるメモリのアクセスサイクル
を示すタイミングチヤート、第５図乃至第８図は
第１図の一実施例の動作を説明するためのタイミ
ングチヤート、第９図は従来のメモリアクセス装
置のブロツク図である。
２０１……マイクロプロセツサ、２０２……メ
モリ、２０３……アドレスラツチ回路、２０４，
２１３……セレクタ、２０５，２１４……バツフ
ア、２０６……ラツチ回路、２０７……バス切換
制御回路、２０８……アドレスバス、２０９……
（マイクロプロセツサの）データバス、２１０…
…（メモリの）データバス。
Figure 1 is a block diagram of one embodiment of the present invention;
The figure is a block diagram of the main part of FIG. 1, FIGS. 3 and 4 are timing charts showing the access cycle of the memory used in FIG. 1, and FIGS. 5 to 8 are an example of the embodiment shown in FIG. 1. FIG. 9 is a timing chart for explaining the operation of the conventional memory access device. 201...Microprocessor, 202...Memory, 203...Address latch circuit, 204,
213... Selector, 205, 214... Buffer, 206... Latch circuit, 207... Bus switching control circuit, 208... Address bus, 209...
(microprocessor) data bus, 210...
...(memory) data bus.
Claims (1)
ロセツサと、このマイクロプロセツサのメモリリ
ードまたはメモリライトの１マシンサイクル内で
複数回のメモリリードサイクルまたは複数回のメ
モリライトサイクルが可能な速度を有する４ｍビ
ツト以下のｎビツトメモリと、このメモリのアド
レス端子と接続され、前記マイクロプロセツサよ
り出力されるアドレスデータをラツチするアドレ
スラツチ回路と、バイトアクセス時には前記メモ
リが前記１マシンサイクルにおいて少なくとも１
回アクセスされるようにメモリ制御信号を送出し
、ワードアクセス時には８ｍ／ｎ回アクセスされ
るようにメモリ制御信号を送出するメモリ制御部
と、バイトアクセス時には前記メモリのデータバ
スを前記マイクロプロセツサのデータバスの一部
と接続し、ワードアクセス時には前記メモリのデ
ータバスのデータを８ｍ／ｎ回取込んで夫々前記
マイクロプロセツサのデータバスへ分配して送出
するか、前記マイクロプロセツサのデータバスの
データを８ｍ／ｎ回に分けて送出するかの少なく
とも一方を行うデータバス変換部とを具備するメ
モリアクセス装置。 8m (m = 1, 2, 3,...) bit microprocessor and multiple memory read cycles or multiple memory write cycles are possible within one machine cycle of memory read or memory write of this microprocessor. an n-bit memory having a speed of 4m bits or less; an address latch circuit connected to the address terminal of this memory to latch address data output from the microprocessor; 1
a memory control unit that sends out a memory control signal so that it will be accessed twice, and sends out a memory control signal so that it will be accessed 8m/n times during a word access; It is connected to a part of the data bus, and at the time of word access, the data on the data bus of the memory is fetched 8 m/n times and distributed and sent to the data bus of the microprocessor respectively, or the data bus of the microprocessor is a data bus conversion section that performs at least one of transmitting the data divided into 8m/n times.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986026598U JPS62146247U (en) | 1986-02-27 | 1986-02-27 | |
| KR2019870002362U KR900008967Y1 (en) | 1986-02-27 | 1987-02-27 | Memory access apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986026598U JPS62146247U (en) | 1986-02-27 | 1986-02-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62146247U true JPS62146247U (en) | 1987-09-16 |
Family
ID=30827829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986026598U Pending JPS62146247U (en) | 1986-02-27 | 1986-02-27 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS62146247U (en) |
| KR (1) | KR900008967Y1 (en) |
-
1986
- 1986-02-27 JP JP1986026598U patent/JPS62146247U/ja active Pending
-
1987
- 1987-02-27 KR KR2019870002362U patent/KR900008967Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR870013829U (en) | 1987-09-10 |
| KR900008967Y1 (en) | 1990-09-29 |
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