JP2581484B2 - Data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing system having a logic LSI such as a microprocessor, and more particularly to a system employing a bus control method suitable for realizing a high-speed bus cycle.

[0002]

2. Description of the Related Art The above-mentioned logic LSI which is expected to have a large system configuration with a conventional microprocessor or the like.
Since it is necessary to make bus connections with various devices having different access times, an asynchronous bus control method is introduced.

A bus control method using an asynchronous system controls communication via a bus between a logic LSI and a device to be accessed by a shake hand system. In the bus cycle, first, an access address is output on the logic LSI side, and in the write cycle, data is also output. The accessed device sends a bus cycle end signal to the logic LSI to notify the timing of communication end. After receiving this signal, the logic LSI reads data from the bus in the read cycle and ends the bus cycle.

As described above, in the asynchronous bus control, before the accessed device sends data onto the bus or receives data from the bus, it predicts the end timing of the bus cycle in advance and generates a bus cycle end signal. It is necessary to send out to the logic LSI side.

FIG. 2 shows an example of a timing chart of bus control according to this type of method, and FIG. 3 shows an example of the configuration around the logic LSI 14. AV (address valid: Addres) in FIG.
The s Valid) signal indicates that the address output by the logic LSI has become valid, and the DC (Data Complete) signal is a bus cycle end signal by a peripheral device.

As this type of device, there is a 16-bit microcomputer 68000 or the like. Other similar technologies are disclosed in Japanese Utility Model Application Laid-Open No.
There is one described in JP-A-118850.

[0007]

In the above prior art, no consideration is given to the generation delay of the bus cycle end signal outside the chip, and even if the access time of the external device is shortened, the bus cycle end is not considered. There was a problem that the bus cycle could not be sped up due to signal generation delay.

Further, in the devices disclosed in Japanese Utility Model Laid-Open No. 60-95563 and Japanese Patent Laid-Open No. 61-118850, the timing of generating a bus cycle end signal is set for all external devices. No consideration has been given to the case where an external device that is not connected is connected. In particular, since the timing of the end of the bus cycle is not constant in the asynchronous external device, it is almost impossible to set the timing of the end of the bus cycle before connecting such a device. An object of the present invention is to realize a system in which a bus occupation time is reduced in a data processing system including various devices.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to provide a processor, an area designation register 1 into which address designation information is written by the processor, and a match for comparing an access address with the address designation information stored in the area designation register. Logic LS having detection circuit 2 on chip
I, a first device corresponding to the addressing information stored in the area specifying register, and a second device not corresponding to the addressing information stored in the area specifying register; 2 indicates a match, the bus cycle is terminated in response to the output signal of the match detection circuit 2. If the match detection circuit 2 does not indicate a match, the bus cycle is terminated by a bus cycle end signal from outside the chip. The data processing system is characterized in that the bus cycle is terminated in response, and the addressing information stored in the area designation register is written by the processor executing an instruction.

In brief, when a specific device is accessed, a bus cycle end signal is automatically generated, and when another device is accessed, a bus cycle signal relating to the device is used. And further, by writing the address of the specific device by executing the instruction by the processor,
The above objective is accomplished.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.

An address space for internally generating a bus cycle end signal at the time of access is designated by an area designation register 1. The writing of the designation information to this register 1 is as follows.
As in the case of a control register such as a condition code register of a microprocessor or the like, it is performed by an instruction.
The address space specified by the register 1 is the match detection circuit 2
Is input to The coincidence detecting circuit 2 checks whether or not the access address 6 exists in the address space specified by the register 1. The access address 6 is a signal obtained by synchronizing the address 3 output from the chip at the time of memory access through the latch 5 with a control signal from the timing generation circuit 4.

A circuit configuration example of the area designation register 1 and the coincidence detection circuit 2 will be described with reference to FIG.

The area designating register 1 comprises a register 7 for designating an address space and a mask register 8 for defining the validity of each bit designated by the register 7. If all bits in the mask register 8 are set to "1", a signal indicating that the access address is within the specified area (signal 9 is "1") is output regardless of the value of the address 6. You. In this case, the bus cycle end signal is automatically generated inside the chip. Conversely, if all bits in the mask register 8 are set to "0", a signal 9 = "0" indicating that the access address 6 is out of the specified area is provided unless the access address 6 completely matches the value of the register 7. Is output. A plurality of pairs of the area designation register 1 and the coincidence detection circuit 2 can be set, and in this case, the outputs 9 of the coincidence detection circuit 2 may be combined by OR logic.
Also, this circuit configuration can be realized by an associative memory.

The output 9 of the coincidence detecting circuit 2 is used to notify the peripheral devices of the chip that the data is within the designated area.
Cycle) signal is output outside the chip,
The signal is output as a signal 11 in accordance with the timing of a bus cycle end signal DC (Data Complete) 13 which is the minimum bus cycle.

This signal 11 is a bus cycle end signal 13
And an OR logic is obtained and input to the bus cycle control circuit. Since the internal bus cycle end signal generator of the present invention is connected in parallel with the bus cycle end signal DC (13) generator configured externally, the DC signal 13
There is no obstacle to adopting a system configuration that generates

FIG. 5 shows a timing chart when the bus cycle end signal is internally generated in this embodiment. The bus cycle is fixed to the minimum bus cycle, and the SC signal 10 indicating that the bus is within the designated area is asserted.

[0018]

According to the present invention, a minimum bus cycle response is possible without externally generating a bus cycle end signal in communication with a device which can be accessed at a sufficiently high speed. The best bus control can be performed according to the above, and the data transfer for determining the performance of the logic LSI can be speeded up.

[0019]

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing chart example of a bus cycle according to a conventional asynchronous system.

FIG. 3 is a configuration example around a chip for realizing a conventional asynchronous bus control.

FIG. 4 shows main components of an embodiment of the present invention.

FIG. 5 is a timing chart of bus control according to the embodiment of the present invention.

[Explanation of symbols]

1. area designation register, 2. address space coincidence detection circuit, 6. access address, 10. area display signal, 13. bus cycle end signal, 14. logic LSI, 15. delay circuit 16 and 17 decoders, 18 peripheral control devices, etc. 19 memories, 2
0 Data bus.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Kuwawa Aoki 1-280, Higashi-Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Inside the Musashi Factory (56) References Japanese Utility Model Showa 60-95653 (JP, U)

Claims (1)

(57) [Claims] An on-chip processor includes a processor, an area specifying register 1 into which addressing information is written by the processor, and a coincidence detecting circuit 2 for comparing an access address with address specifying information stored in the area specifying register. A logic LSI, a first device corresponding to the addressing information stored in the area specifying register, and a second device not corresponding to the addressing information stored in the area specifying register. If the detection circuit 2 indicates a match, the bus cycle ends in response to the output signal of the match detection circuit 2, and if the match detection circuit 2 does not indicate a match, the bus cycle from outside the chip ends. The bus cycle is completed in response to the signal, and the addressing information stored in the area specifying register is stored in the above-described processing area. A data processing system, wherein the data is written by a processor executing an instruction.