JPH0267288U - - Google Patents
Info
- Publication number
- JPH0267288U JPH0267288U JP14611488U JP14611488U JPH0267288U JP H0267288 U JPH0267288 U JP H0267288U JP 14611488 U JP14611488 U JP 14611488U JP 14611488 U JP14611488 U JP 14611488U JP H0267288 U JPH0267288 U JP H0267288U
- Authority
- JP
- Japan
- Prior art keywords
- output
- register
- adder
- comparator
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第１図は本考案の一実施例を示す図、第２図は
本考案の各部の信号を示す図、第３図は従来の信
号検出装置を示す図、第４図は従来の装置の各部
の信号を示す図である。
図中、１，２，３はレジスタ、４，５は加算器
、６は平均値検出器、７，１０は乗算器、８，１
１はコンパレータ、９は最大値検出器、１２はセ
レクタ、Ｘ０〜Ｘ８は各部の信号である。なお、
図中同一あるいは相当部分は同一符号を付して示
してある。
Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing signals of various parts of the present invention, Fig. 3 is a diagram showing a conventional signal detection device, and Fig. 4 is a diagram showing various parts of the conventional device. FIG. In the figure, 1, 2, 3 are registers, 4, 5 are adders, 6 is an average value detector, 7, 10 are multipliers, 8, 1
1 is a comparator, 9 is a maximum value detector, 12 is a selector, and X 0 to X 8 are signals of each part. In addition,
Identical or corresponding parts in the figures are designated by the same reference numerals.
Claims (1)
スタと、前記第１のレジスタの出力を１段遅延す
る第２のレジスタと、前記第２のレジスタの出力
を連続的に遅延するＮ段の第３のレジスタと、前
記第１のレジスタのＮ個の出力を加算する第１の
加算器と、前記第３のレジスタのＮ個の出力を加
算する第２の加算器と、前記第１の加算器の出力
と、前記第２の加算器の出力の平均値を算出する
平均値算出器と、前記第１の加算器の出力と、前
記第２の加算器の出力の最大値を算出する最大値
検出器と、前記平均値算出器の出力と係数Ｋを乗
算する第１の乗算器と、前記最大値検出器の出力
と係数Ｋとを乗算する第２の乗算器と、前記第２
のレジスタの出力と、前記第１の乗算器の出力を
比較する第１のコンパレータと、前記第２のレジ
スタの出力と、前記第２の乗算器の出力を比較す
る第２のコンパレータと、前記第１のコンパレー
タの出力と、前記第２のコンパレータの出力を切
換えるセレクタを備えたことを特徴とする信号検
出装置。 N stages of first registers that continuously delay an input signal, a second register that delays the output of the first register by one stage, and N stages that continuously delay the output of the second register. a third register, a first adder that adds the N outputs of the first register, a second adder that adds the N outputs of the third register, and a second adder that adds the N outputs of the third register; an average value calculator that calculates an average value of the output of the adder and the output of the second adder; and a maximum value of the output of the first adder and the output of the second adder. a first multiplier that multiplies the output of the average value calculator by a coefficient K; a second multiplier that multiplies the output of the maximum value detector by the coefficient K; 2
a first comparator that compares the output of the register and the output of the first multiplier; a second comparator that compares the output of the second register and the output of the second multiplier; A signal detection device comprising a selector that switches between the output of the first comparator and the output of the second comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14611488U JPH0267288U (en) | 1988-11-09 | 1988-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14611488U JPH0267288U (en) | 1988-11-09 | 1988-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0267288U true JPH0267288U (en) | 1990-05-22 |
Family
ID=31415302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14611488U Pending JPH0267288U (en) | 1988-11-09 | 1988-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0267288U (en) |
-
1988
- 1988-11-09 JP JP14611488U patent/JPH0267288U/ja active Pending
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