JPS63163026U - - Google Patents
Info
- Publication number
- JPS63163026U JPS63163026U JP5403187U JP5403187U JPS63163026U JP S63163026 U JPS63163026 U JP S63163026U JP 5403187 U JP5403187 U JP 5403187U JP 5403187 U JP5403187 U JP 5403187U JP S63163026 U JPS63163026 U JP S63163026U
- Authority
- JP
- Japan
- Prior art keywords
- multiplier
- output
- register
- adder
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Complex Calculations (AREA)
Description
第１図は本考案に係るデジタルフイルタの一実
施例を示すブロツク図、第２図は従来のデジタル
フイルタの構成を示すブロツク図である。
１０…マルチプレクサ、１１…第１のレジスタ
、１２…レジスタ群、１３…乗算器、１４…第１
の乗算器群、１５，１８…加算器、１６…遅延器
、１７…第２の乗算器群。
FIG. 1 is a block diagram showing an embodiment of a digital filter according to the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional digital filter. DESCRIPTION OF SYMBOLS 10... Multiplexer, 11... First register, 12... Register group, 13... Multiplier, 14... First
15, 18...adder, 16...delay unit, 17...second multiplier group.
Claims (1)
フトされるレジスタ群と、時系列データが入力さ
れこれら時系列データを交互に前記レジスタ群お
よび第１のレジスタに入力するマルチプレクサと
、前記レジスタ群を構成する前記複数のレジスタ
の各々に格納されているデータに所定の値を乗算
して出力する第１および第２の乗算器群と、前記
第１のレジスタに格納されているデータに所定の
値を乗算して出力する第１の乗算器と、この第１
の乗算器の出力および前記第１の乗算器群の出力
を加算する第１の加算器と、この第１の加算器の
出力を所定の時間遅延させる遅延器と、この遅延
器の出力および前記第２の乗算器の出力を加算す
る第２の加算器とを有することを特徴とするデジ
タルフイルタ。 The register group includes a register group in which a plurality of registers are connected in series and data is shifted in order, and a multiplexer to which time-series data is input and which alternately inputs the time-series data to the register group and the first register. first and second multiplier groups that multiply data stored in each of the plurality of registers by a predetermined value and output the result; and multiply the data stored in the first register by a predetermined value. a first multiplier that outputs
a first adder that adds the output of the multiplier and the output of the first multiplier group; a delay device that delays the output of the first adder by a predetermined time; A digital filter comprising a second adder that adds the outputs of the second multiplier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5403187U JPH0625055Y2 (en) | 1987-04-09 | 1987-04-09 | Digital filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5403187U JPH0625055Y2 (en) | 1987-04-09 | 1987-04-09 | Digital filter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63163026U true JPS63163026U (en) | 1988-10-25 |
| JPH0625055Y2 JPH0625055Y2 (en) | 1994-06-29 |
Family
ID=30880643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5403187U Expired - Lifetime JPH0625055Y2 (en) | 1987-04-09 | 1987-04-09 | Digital filter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0625055Y2 (en) |
-
1987
- 1987-04-09 JP JP5403187U patent/JPH0625055Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0625055Y2 (en) | 1994-06-29 |
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