JPS6432600U

JPS6432600U -

Info

Publication number: JPS6432600U
Application number: JP12680587U
Authority: JP
Priority date: 1987-08-20
Filing date: 1987-08-20
Publication date: 1989-03-01

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例に係る残響付加装置
の原理ブロツク図、第２図は本考案の一実施例に
係る残響付加装置の具体的構成を示すブロツク図
、第３図は第２図の音色パラメータメモリ２５の
内部構成を示す図、第４図は第２図の音色パラメ
ータメモリ２６の内部構成を示す図、第５図は残
響付加装置の処理動作を示すフローチヤート、第
６図は第２図の波形データメモリの書き込みアド
レスの説明図である。１，２，３，４……遅延回路、５，６，７，８
，１４……乗算器、９，１０，１１，１２，１３
，１５……加算器、２１……プログラムメモリ、
２５，２６……音色パラメータメモリ、２９……
演算回路、３０……乗算回路、３３……波形デー
タメモリ。 FIG. 1 is a principle block diagram of a reverberation adding device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration of a reverberation adding device according to an embodiment of the present invention, and FIG. 4 is a diagram showing the internal configuration of the timbre parameter memory 25 in FIG. 2, FIG. 5 is a flowchart showing the processing operation of the reverberation adding device, and FIG. 2 is an explanatory diagram of write addresses of the waveform data memory in FIG. 2. FIG. 1, 2, 3, 4...Delay circuit, 5, 6, 7, 8
, 14... Multiplier, 9, 10, 11, 12, 13
, 15...Adder, 21...Program memory,
25, 26...Tone parameter memory, 29...
Arithmetic circuit, 30... Multiplication circuit, 33... Waveform data memory.

Claims

[Claims for Utility Model Registration] A plurality of delay means that are connected in parallel with a common input and that delay and output input signal data, and a plurality of delay means that feed back the outputs of the plurality of delay means to their respective input sides. a first feedback means; an adding means for adding the outputs of the plurality of delay means; and feeding back the output of the adding means to a common input side such that the feedback amount has a different sign from the feedback amount of the first feedback means. A reverberation adding device comprising: a set second feedback means;