JPH0370655U - - Google Patents
Info
- Publication number
- JPH0370655U JPH0370655U JP12953889U JP12953889U JPH0370655U JP H0370655 U JPH0370655 U JP H0370655U JP 12953889 U JP12953889 U JP 12953889U JP 12953889 U JP12953889 U JP 12953889U JP H0370655 U JPH0370655 U JP H0370655U
- Authority
- JP
- Japan
- Prior art keywords
- start address
- memory
- circuit
- memory blocks
- arithmetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第1図は本考案に係るメモリセレクト装置の一
実施例のブロツク図、第2図は従来のメモリセレ
クト装置のブロツク図である。
4…入力アドレス信号、9…先頭アドレス発生
回路、10…先頭アドレス信号、11…加算器、
12…入力アドレス信号4と先頭アドレス信号1
0との差信号、13…デコーダ、14…ブロツク
セレクト信号。
FIG. 1 is a block diagram of an embodiment of a memory select device according to the present invention, and FIG. 2 is a block diagram of a conventional memory select device. 4...Input address signal, 9...Start address generation circuit, 10...Start address signal, 11...Adder,
12...Input address signal 4 and start address signal 1
13...decoder, 14...block select signal.
Claims (1)
ツク全てを通じての先頭アドレスを発生する先頭
アドレス発生回路と、 入力アドレスと前記先頭アドレスとの差を求め
る演算回路と、 該演算回路出力をデコードして前記複数のメモ
リブロツクに対するセレクト信号を発生するデコ
ーダと、 を備えているメモリセレクト装置。[Claims for Utility Model Registration] A start address generation circuit that generates a start address through all of a plurality of memory blocks included in one memory board, an arithmetic circuit that calculates the difference between an input address and the start address, and the arithmetic operation. A memory selection device comprising: a decoder that decodes a circuit output to generate selection signals for the plurality of memory blocks.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12953889U JPH0370655U (en) | 1989-11-06 | 1989-11-06 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12953889U JPH0370655U (en) | 1989-11-06 | 1989-11-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0370655U true JPH0370655U (en) | 1991-07-16 |
Family
ID=31677161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12953889U Pending JPH0370655U (en) | 1989-11-06 | 1989-11-06 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0370655U (en) |
-
1989
- 1989-11-06 JP JP12953889U patent/JPH0370655U/ja active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6454484U (en) | ||
JPH0370655U (en) | ||
JPS6188327U (en) | ||
JPH02141117U (en) | ||
JPS60584U (en) | Alarm Clock | |
JPS5836800U (en) | Speech synthesis output device | |
JPH0277747U (en) | ||
JPS6160302U (en) | ||
JPS6025281U (en) | mixing circuit | |
JPH0397237U (en) | ||
JPH01100240U (en) | ||
JPH03114887U (en) | ||
JPH0385587U (en) | ||
JPH01142224U (en) | ||
JPH01178694U (en) | ||
JPH0290585U (en) | ||
JPS5832495U (en) | audio time clock | |
JPS63183635U (en) | ||
JPH0210633U (en) | ||
JPS5847945U (en) | Request signal processing circuit | |
JPS63108216U (en) | ||
JPS6013497U (en) | multi alarm clock | |
JPS6439536U (en) | ||
JPH02104448U (en) | ||
JPS5947893U (en) | Pointer type melody clock |