JPH0370655U - - Google Patents

Info

Publication number
JPH0370655U
JPH0370655U JP12953889U JP12953889U JPH0370655U JP H0370655 U JPH0370655 U JP H0370655U JP 12953889 U JP12953889 U JP 12953889U JP 12953889 U JP12953889 U JP 12953889U JP H0370655 U JPH0370655 U JP H0370655U
Authority
JP
Japan
Prior art keywords
start address
memory
circuit
memory blocks
arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12953889U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12953889U priority Critical patent/JPH0370655U/ja
Publication of JPH0370655U publication Critical patent/JPH0370655U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係るメモリセレクト装置の一
実施例のブロツク図、第2図は従来のメモリセレ
クト装置のブロツク図である。 4…入力アドレス信号、9…先頭アドレス発生
回路、10…先頭アドレス信号、11…加算器、
12…入力アドレス信号4と先頭アドレス信号1
0との差信号、13…デコーダ、14…ブロツク
セレクト信号。
FIG. 1 is a block diagram of an embodiment of a memory select device according to the present invention, and FIG. 2 is a block diagram of a conventional memory select device. 4...Input address signal, 9...Start address generation circuit, 10...Start address signal, 11...Adder,
12...Input address signal 4 and start address signal 1
13...decoder, 14...block select signal.

Claims (1)

【実用新案登録請求の範囲】 一のメモリボードに含まれる複数のメモリブロ
ツク全てを通じての先頭アドレスを発生する先頭
アドレス発生回路と、 入力アドレスと前記先頭アドレスとの差を求め
る演算回路と、 該演算回路出力をデコードして前記複数のメモ
リブロツクに対するセレクト信号を発生するデコ
ーダと、 を備えているメモリセレクト装置。
[Claims for Utility Model Registration] A start address generation circuit that generates a start address through all of a plurality of memory blocks included in one memory board, an arithmetic circuit that calculates the difference between an input address and the start address, and the arithmetic operation. A memory selection device comprising: a decoder that decodes a circuit output to generate selection signals for the plurality of memory blocks.
JP12953889U 1989-11-06 1989-11-06 Pending JPH0370655U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12953889U JPH0370655U (en) 1989-11-06 1989-11-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12953889U JPH0370655U (en) 1989-11-06 1989-11-06

Publications (1)

Publication Number Publication Date
JPH0370655U true JPH0370655U (en) 1991-07-16

Family

ID=31677161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12953889U Pending JPH0370655U (en) 1989-11-06 1989-11-06

Country Status (1)

Country Link
JP (1) JPH0370655U (en)

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