JPH03114887U

JPH03114887U -

Info

Publication number: JPH03114887U
Application number: JP2211090U
Authority: JP
Priority date: 1990-03-07
Filing date: 1990-03-07
Publication date: 1991-11-26

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を示す回路構成図、
第２図ａ，ｂは同実施例の動作を説明するための
係数ビツトと制御信号との関係を示す図、第３図
ａ，ｂは従来の並列乗算回路を示すブロツク図で
ある。１１……デコーダ、２０ａ〜２０ｅ，２１ａ〜
２１ｅ……ＥＸオア回路、２２〜２７……アナロ
グスイツチ、３０……加算器、３１〜３７……フ
ルアダー。 FIG. 1 is a circuit diagram showing an embodiment of the present invention;
2A and 2B are diagrams showing the relationship between coefficient bits and control signals for explaining the operation of the same embodiment, and FIGS. 3A and 3B are block diagrams showing a conventional parallel multiplication circuit. 11...Decoder, 20a-20e, 21a-
21e...EX OR circuit, 22-27...analog switch, 30...adder, 31-37...full adder.

Claims

[Scope of utility model registration request]

control signal generating means for generating a control signal corresponding to coefficient data; first and second switch groups to which the data to be operated are input and whose switching is controlled by control signals output from the control signal generating means; Means for multiplying the operand data input to the first and second switch groups by ²ⁿ for each group by shifting the operand data input to the first switch group; and inverting the operand data input to the first switch group in accordance with the control signal. An arithmetic circuit comprising: signal inverting means for adding data selected by the first and second switch groups; and addition means for adding data selected by the first and second switch groups.