JPH0290895U - - Google Patents

Description

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the configuration of the main parts of a central processing unit for an electronic musical instrument according to an embodiment of this invention, Figure 2 is a map showing the internal structure of the RAM, and Figure 3 is a diagram of the timing generator. This is a time chart of the generated timing signals. 1... Timing generator, 2... Program ROM, 4... Decoder, 5... RAM, 8
...Addition/subtraction circuit.

Claims (1)

[Claims for Utility Model Registration] (1) A first group of readable and writable registers having a number of bits suitable for processing control input of a musical instrument, and a second group having a number of bits suitable for generating a musical tone signal. A read/write storage device for an electronic musical instrument, comprising a second group of readable/writable registers. (2) A first group of readable and writable registers having a number of bits suitable for processing musical instrument control inputs and a second group of readable and writable registers having a number of bits suitable for generating musical tone signals. an arithmetic circuit device, a program storage device that stores a program, and an operation control circuit that decodes each instruction of the program and controls the operation of each of the devices; Under the control of the operation control circuit, the arithmetic circuit device performs not only operations between registers in the first register group and operations between registers in the second register group, but also operations between registers in the first register group. A central processing unit for an electronic musical instrument, characterized in that an operation can also be executed between a register in the register group and a register in the second register group. (3) In the central processing unit for an electronic musical instrument according to claim 2, the registers belonging to the first register group have a first length, and the registers belonging to the second register group have a length longer than the first register group. the second longer than the length
When performing an operation using a register belonging to the first register group as an operand and using a register belonging to the second register group as an operator, the arithmetic circuit device has a length of The upper bits of the register are invalidated to match the processing length to the length of the operand register, and conversely, the register belonging to the first register group is used as the operator, and the register belonging to the second register group is used as the operator. A central processing unit for an electronic musical instrument, characterized in that when performing an operation as an operand, a zero is added to a bit position higher than the register of the operator to match the length of the register of the operand.