JPH01111299U - - Google Patents
Info
- Publication number
- JPH01111299U JPH01111299U JP15706687U JP15706687U JPH01111299U JP H01111299 U JPH01111299 U JP H01111299U JP 15706687 U JP15706687 U JP 15706687U JP 15706687 U JP15706687 U JP 15706687U JP H01111299 U JPH01111299 U JP H01111299U
- Authority
- JP
- Japan
- Prior art keywords
- data
- creation
- circuit
- calculation
- creating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 8
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
Description
第1図は本考案の一実施例に係る電子楽器のデ
ータ作成装置の回路ブロツク図、第2図及び第3
図はその回路の動作を示すタイムチヤート、第4
図は制御信号SFT0、SFT1,SFT2の説
明図、第5図はフルアダー2の具体的回路図、第
6図はシフタ5の具体的回路図、第7図は制御信
号作成回路の回路図、第8図aは、フリツプフロ
ツプ41のデータの構成を示す図、同図bは制御
信号作成回路の動作を示すタイムチヤート、第9
図はタイミング信号作成回路の回路図、第10は
上記回路のフリツプフロツプ71のデータの構成
を示す図、第11図は、パラレル/シリアル変換
器9の具体的回路図である。
1……マルチプレクサ、2……フルアダー、5
……シフタ、9……パラレル/シリアル変換器。
FIG. 1 is a circuit block diagram of a data creation device for an electronic musical instrument according to an embodiment of the present invention, and FIGS.
The figure is a time chart showing the operation of the circuit.
5 is a specific circuit diagram of the full adder 2, FIG. 6 is a specific circuit diagram of the shifter 5, FIG. 7 is a circuit diagram of the control signal generation circuit, and FIG. 8a is a diagram showing the data structure of the flip-flop 41, and FIG. 8b is a time chart showing the operation of the control signal generation circuit.
10 is a circuit diagram of a timing signal generating circuit, 10th is a diagram showing the data structure of flip-flop 71 of the above circuit, and FIG. 11 is a specific circuit diagram of parallel/serial converter 9. 1...Multiplexer, 2...Full adder, 5
...Shifter, 9...Parallel/serial converter.
補正 平1.3.1
図面の簡単な説明を次のように補正する。
明細書の第39頁第1行目に「第10は上記回
路の……」とあるを「第10図は上記回路の……
」と補正する。Amendment 1.3.1 The brief description of the drawing is amended as follows. In the first line of page 39 of the specification, it says "Figure 10 shows the above circuit..." instead of "Figure 10 shows the above circuit..."
” he corrected.
Claims (1)
と、 該演算手段により演算された演算結果をパラレ
ルデータとして作成するパラレルデータ作成手段
と、 前記演算結果をシリアルデータとして作成する
シリアルデータ作成手段と、 を有することを特徴とする電子楽器のデータ作成
装置。[Claims for Utility Model Registration] Calculation means for calculating input musical waveform data; parallel data creation means for creating parallel data from the calculation results calculated by the calculation means; and creation of the calculation results as serial data. 1. A data creation device for an electronic musical instrument, comprising: serial data creation means for creating data;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15706687U JPH01111299U (en) | 1987-10-14 | 1987-10-14 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15706687U JPH01111299U (en) | 1987-10-14 | 1987-10-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01111299U true JPH01111299U (en) | 1989-07-26 |
Family
ID=31436179
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15706687U Pending JPH01111299U (en) | 1987-10-14 | 1987-10-14 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01111299U (en) |
-
1987
- 1987-10-14 JP JP15706687U patent/JPH01111299U/ja active Pending
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