JPS61204256U - - Google Patents

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Publication number
JPS61204256U
JPS61204256U JP7283286U JP7283286U JPS61204256U JP S61204256 U JPS61204256 U JP S61204256U JP 7283286 U JP7283286 U JP 7283286U JP 7283286 U JP7283286 U JP 7283286U JP S61204256 U JPS61204256 U JP S61204256U
Authority
JP
Japan
Prior art keywords
integrand
input
dividing
calculation
range
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7283286U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7283286U priority Critical patent/JPS61204256U/ja
Publication of JPS61204256U publication Critical patent/JPS61204256U/ja
Pending legal-status Critical Current

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  • Calculators And Similar Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示す回路ブロツク
図、第２図は第１図中ＲＡＭ２のレジスタ構成図
、第３図は第１図中ＲＡＭ９の被積分関数記憶状
態図、第４図は動作を説明するためのフローチヤ
ート、第５図は上記フローチヤートに伴うレジス
タ状態図である。 １……ＲＯＭ、２……ＲＡＭ、３……ＲＯＭア
ドレス部、４……インストラクシヨンデコーダ、
５……演算回路、７……キー入力部、９……ＲＡ
Ｍ。 FIG. 1 is a circuit block diagram showing an embodiment of the present invention, FIG. 2 is a register configuration diagram of RAM 2 in FIG. 1, FIG. 3 is a storage state diagram of an integrand in RAM 9 in FIG. 1, and FIG. is a flowchart for explaining the operation, and FIG. 5 is a register state diagram accompanying the above flowchart. 1...ROM, 2...RAM, 3...ROM address section, 4...instruction decoder,
5... Arithmetic circuit, 7... Key input section, 9... RA
M.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 被積分関数、定積分範囲及び分割数を入力する
入力手段と、該入力手段から入力された被積分関
数を記憶する記憶手段と、上記入力手段から入力
された定積分範囲を上記入力手段から入力された
分割数に従つて分割する分割手段と、上記記憶手
段に記憶されている被積分関数を順次読み出す読
出手段と、該読出手段から読み出された被積分関
数に基づき上記分割手段で分割された分割範囲毎
に順次積分演算を行なう演算手段とを具備し、被
積分関数を任意に分割して定積分演算を行なうこ
とを特徴とする積分演算機能を有する小型電子式
計算機。 an input means for inputting an integrand, a definite integral range, and a number of divisions; a storage means for storing the integrand input from the input means; and an input means for inputting the definite integral range input from the input means. a dividing means for dividing according to the number of divisions made; a reading means for sequentially reading out the integrand stored in the storage means; 1. A small electronic calculator having an integral calculation function, comprising calculation means for sequentially performing an integral calculation for each divided range, and performing a definite integral calculation by arbitrarily dividing an integrand function.
JP7283286U 1986-05-15 1986-05-15 Pending JPS61204256U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7283286U JPS61204256U (en) 1986-05-15 1986-05-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7283286U JPS61204256U (en) 1986-05-15 1986-05-15

Publications (1)

Publication Number Publication Date
JPS61204256U true JPS61204256U (en) 1986-12-23

Family

ID=30611614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7283286U Pending JPS61204256U (en) 1986-05-15 1986-05-15

Country Status (1)

Country Link
JP (1) JPS61204256U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5426635A (en) * 1977-07-29 1979-02-28 Sharp Corp Electronic desk calculator with function of definite integral

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5426635A (en) * 1977-07-29 1979-02-28 Sharp Corp Electronic desk calculator with function of definite integral

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